ARM PrimeCelL PL320 Technical Reference Manual page 23

Inter-processor communications module

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2.2.2

Channel ID

ARM DDI 0306B

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Interrupt

controller0

AHB

IPCMINT[0]

The IPCM operates as follows:

Core0 has a message to send to Core1. Core0 claims the mailbox by setting bit 0

in the Mailbox Source Register. Core0 then sets bit 1 in the Mailbox Destination

Registers. Finally, Core0 sends the message by writing 01 to the Mailbox Send

When Core1 is interrupted, it reads the Masked Interrupt Status Register for

IPCMINT[1] to determine which mailbox contains the message. Core1 reads the

message in that mailbox, then clears the interrupt and asserts the acknowledge

interrupt by writing 10 to the Mailbox Send Register.

Core0 is interrupted with the acknowledge message, completing the operation.

Core0 then decides whether to retain the mailbox to send another message or

release the mailbox, freeing it up for other cores in the system to use it.

The Channel ID is defined as the one-hot encoded value that corresponds to a specific

interrupt output from the IPCM. An IPCM configured to have 32 interrupt outputs has

32 corresponding Channel IDs. The Channel ID programs the Mailbox Source, Mailbox

Destination, and Mailbox Mask Registers.

Core0

Core1

IPCM

IPCMINT[1]

Figure 2-3 Basic operation

Functional Overview

Interrupt

controller1

2-5

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