Figure 2-8 Back-To-Back Messaging From Core0 To Core1 - ARM PrimeCelL PL320 Technical Reference Manual

Inter-processor communications module

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Table of Contents

ARM DDI 0306B

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IPCM0SOURCE[1:0]

IPCM0DSTATUS[1:0]

IPCM0MODE[1:0]

IPCM0MSTATUS[1:0]

IPCM0SEND[1:0]

IPCM0DR0[31:0]

00000000

IPCMRIS0[3:0]

IPCMRIS1[3:0]

IPCMINT[3:0]

In this example, the following sequence occurs:

Core0 gains control of Mailbox0 and identifies itself as the source core by setting

bit 0 in the IPCM0SOURCE Register.

Core0 enables interrupts to Core0 and Core1 by setting bits 0 and 1 in the

IPCM0MSTATUS Register.

Core0 defines the destination core by setting bit 1 in the IPCM0DSTATUS

Core0 programs the data payload,

Core0 sets bit 0 of the IPCM0SEND Register to send the interrupt to the

destination core.

Core1 reads the IPCMRIS1 Register and reads the data payload.

Core1 optionally updates the data payload for the Acknowledge,

Core1 clears bit 0 and sets bit 1 in the IPCM0SEND Register to provide the

Manual Acknowledge back to Core0.

Core0 reads the IPCMRIS0 Register and reads the data payload.

10.

Core0 programs the data payload for the next message,

11.

Core0 clears bit 1 and sets bit 0 of the IPCM0SEND Register to send the interrupt

to the destination core.

DA7A0000

DA7A1111