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(4)
Timer Gn Channel Mode Register (TMGCMn)
This register specifies the assigned counter (TMGn0 or TMGn1) for the GCCnm register.
Furthermore it specifies the edge detection for the TIGy-input-pins (y = 0 to 5).
This register can be read/written in 16-bit, 8-bit or 1-bit units.
Figure 10-33: Timer Gn Channel Mode Register (TMGCMn)
15
14
13
TMGCM0H TBG4 TBG3 TBG2 TBG1 IEG51 IEG50 IEG41 IEG40 IEG31 IEG30 IEG21 IEG20 IEG11 IEG10 IEG01 IEG00 FFFF 642H 0000H
TMGCM1H TBG4 TBG3 TBG2 TBG1 IEG51 IEG50 IEG41 IEG40 IEG31 IEG30 IEG21 IEG20 IEG11 IEG10 IEG01 IEG00 FFFF 682H 0000H
Bit Position
Bit Name
15 to 12
TBGm
IEGy1,
11 to 4
IEGy0
Remarks: 1. y = 0 to 5
2. m = 1 to 4
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Chapter 10 Timer
12
11
10
9
8
Assigns Capture/Compare registers GCCn1 to GCCn4 to one of the 2 counters
TMGn0 or TMGn1:
0: Set TMGn0 as the corresponding counter to GCCnm register and TIGm/
TOGnm-pin
1: Set TMGn1 as the corresponding counter to GCCnm register and TIGm/
TOGnm-pin
Specifies the valid edge of external capture signal input pin (TIGm) for the
capture register performing capture-match with the assigned counter TMGn0 or
TMGn1:
IEGy1
IEGy0
0
0
1
1
Preliminary User's Manual U15839EE1V0UM00
7
6
5
4
3
Function
0
Falling edge
1
Rising edge
0
No edge detection performed
1
Both rising and falling edges
2
1
0
Address
Valid Edge
Initial
value
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