NEC V850E/CA2 JUPITER Preliminary User's Manual page 153

(d) During read (address setup wait, idle state insertion)
(when byte access with 8-bit bus width or when byte/half word access with 16-bit bus width)
System CLK
A0 to A23 (output)
CSn (output)
RD (output)
UWR (output)
LWR (output)
D0 to D7 (I/O)
D0 to D15 (I/O)
WAIT (input)
Remarks: 1. The circles
2. The broken line indicates the high-impedance state.
3. CSn = CS0, CS3 and CS4
Chapter 5 Memory Access Control Function
Figure 5-6: Page ROM Access Timing (4/4)
TASW T1
Off-page address
indicate the sampling timing.
Preliminary User's Manual U15839EE1V0UM00
T2 TASW TO1
Data
TO2 TI
On-page address
Data
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