Figure 10-6: Timer C control Register 1 (TMCC01) (2/2)
Bit Position
Bit name
3
CLR
1
CMS1
0
CMS0
Chapter 10 Timer
Enables/disables TMC0 clearing during compare operation.
0: Disable clearing.
1: Enable clearing (TMC0 is cleared when CCC00 and TMC0 match during com-
pare operation).
Selects operation mode of capture/compare register (CCC01).
0: Register operates as capture register.
1: Register operates as compare register.
Selects operation mode of capture/compare register (CCC00).
0: Register operates as capture register.
1: Register operates as compare register.
Preliminary User's Manual U15839EE1V0UM00
Function
281