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8.2.1 Operation
If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers con-
trol to the handler routine:
(1)
Saves the restored PC to FEPC.
(2)
Saves the current PSW to FEPSW.
(3)
Writes exception code 0010H to the higher halfword (FECC) of ECR.
(4)
Sets the NP and ID bits of the PSW and clears the EP bit.
(5)
Sets the handler address corresponding to the non-maskable interrupt to the PC, and transfers
control.
The processing configuration of a non-maskable interrupt is shown in Figure 8-2.
Figure 8-2: Processing Configuration of Non-Maskable Interrupt
acknowledgement
CPU processing
206
Chapter 8 Interrupt/Exception Processing Function
NMI input
INTC
Non-maskable interrupt
request
PSW.NP
FEPC
FEPSW
ECR.FECC ← Exception
PSW.NP
PSW.EP
PSW.ID
PC
Interrupt service
Preliminary User's Manual U15839EE1V0UM00
1
0
←
Restored PC
← PSW
code
← 1
← 0
← 1
← NMI-Handler
address
Interrupt request pending
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