NEC V850E/CA2 JUPITER Preliminary User's Manual page 414

Chapter 13 Serial Interface Function
Figure 13-36: Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2)
(b) When CKP bit = 1, DAP bit = 1
Input clock
SCK0n (input/output)
SI0n (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO0n (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Reg_R/W
INTCSIn
interrupt
CSOT bit
Delay
Remarks: 1. n = 0 to 2
2. Reg_R/W:Internal signal. This signal indicates that receive data buffer register (SIRBn/
SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was performed.
Preliminary User's Manual U15839EE1V0UM00
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