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13.3.3 Control registers
(1)
Clocked serial interface mode registers (CSIM0 to CSIM2)
The CSIMn register controls the CSI0n operation (n = 0 to 2).
These registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only).
Figure 13-22: Clocked Serial Interface Mode Registers (CSIM0 to CSIM2)
7
6
CSIM0
CSIE
TRMD
CSIM1
CSIE
TRMD
CSIM2
CSIE
TRMD
Bit Position Bit Name
7
CSIE
6
TRMD
5
CCL
4
DIR
3
CSIT
2
AUTO
0
CSOT
Remark:
n = 0 to 2
Caution:
Overwriting the TRMD, CCL, DIR, CSIT, and AUTO bits of the CSIMn register can be
done only when the CSOT bit = 0. If these bits are overwritten at any other time, the
operation cannot be guaranteed.
Chapter 13 Serial Interface Function
5
4
CCL
DIR
CCL
DIR
CCL
DIR
Enables/disables CSI0n operation.
0: Disable CSI0n operation.
1: Enable CSI0n operation.
The internal CSI0n circuit can be reset asynchronously by setting the CSIE bit to 0. For
SCK0n
the
and SO0n pin output status when the CSIE bit = 0, refer to 13.3.5 "Output
pins" on page 422.
Specifies transmission/reception mode.
0: Receive-only mode
1: Transmission/reception mode
When the TRMD bit = 0, receive-only transfer is performed and the SO0n pin output is
fixed to low level. Data reception is started by reading the SIRBn register.
When the TRMD bit = 1, transmission/reception is started by writing data to the SOTBn
register.
Specifies data length.
0: 8 bits
1: 16 bits
Specifies transfer direction mode (MSB/LSB).
0: First bit of transfer data is MSB
1: First bit of transfer data is LSB
Controls delay of interrupt request signal.
0: No delay
1: Delay mode (interrupt request signal is delayed 1/2 cycle).
Caution: The delay mode (CSIT bit = 1) is effective only in the master mode
(CKS2 to CKS0 bits of the CSICn register are not 111B). In the slave
mode (CKS2 to CKS0 bits are 111B), do not set the delay mode.
single
Specifies
transfer mode or repeat transfer mode.
single
0:
transfer mode
1: Repeat transfer mode
Flag indicating transfer status.
0: Idle status
1: Transfer execution status
Caution: The CSOT bit is cleared (0) by writing 0 to the CSIE bit.
Preliminary User's Manual U15839EE1V0UM00
3
2
1
CSIT
AUTO
0
CSIT
AUTO
0
CSIT
AUTO
0
Function
0
Address
CSOT
FFFF FD00H
CSOT
FFFF FD40H
CSOT
FFFF FD80H
Initial
value
00H
00H
00H
395
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