Power Save Mode Register (Psm); Figure 9-16: Power Save Mode Register (Psm) - NEC V850E/CA2 JUPITER Preliminary User's Manual

9.5.2 Power Save Mode Register (PSM)

This is an 8-bit register that control the power save mode and sub-oscillator control.
This register can be read or written in 8-bit or 1-bit units.
7
PSM 0 CMODE
Bit name
Calibration mode control bit
0: Calibration timer clock is f
CMODE
1: Calibration timer clock is output from Main-oscillator clock input
Main clock oscillator enable control bit
1: Main oscillator remains stopped after sub-Watch mode release. The CPU will start from sub-
clock.
0: Main oscillator will be enabled after sub-Watch mode release and used for CPU clock gener-
OSCDIS
ation after the oscillation stabilization counter expires.
If this bit is cleared after sub-Watch mode release, the main oscillator will start. After the oscilla-
tion stabilization time expires, the main oscillator can be used as system clock source by setting
the PCC register accordingly.
Standby mode specification bits
PSM1
0
0
PSM1, PSM0
1
1
270
Chapter 9 Clock Generator

Figure 9-16: Power Save Mode Register (PSM)

6 5 4
0 0
PCLK
PSM0
0 IDLE
1 STOP
0 WATCH
Sub-oscillator WATCH mode (Main oscillator shut-down). This mode
1 can only be enabled if SUBEN is "1". Otherwise normal WATCH mode
is forced.
Preliminary User's Manual U15839EE1V0UM00
3 2 1
OSCDIS 0 PSM1
Function
Standby Mode
0 Address
PSM0 FFFFF820H
Initial
value
00H