Table 14-2: Can Message Buffer Registers Layout - NEC V850E/CA2 JUPITER Preliminary User's Manual

Address Offset
Symbol
Note 1, 2
(m × 20H) + 800H
M_EVTm0
(m × 20H) + 801H
M_EVTm1
(m × 20H) + 802H
M_EVTm2
(m × 20H) + 803H
M_EVTm3
(m × 20H) + 804H
M_DLCm
(m × 20H) + 805H
M_CTRLm
(m × 20H) + 806H
M_TIMEm
(m × 20H) + 808H
M_DATAm0
(m × 20H) + 809H
M_DATAm1
(m × 20H) + 80AH
M_DATAm2
(m × 20H) + 80BH
M_DATAm3
(m × 20H) + 80CH
M_DATAm4
(m × 20H) + 80DH
M_DATAm5
(m × 20H) + 80EH
M_DATAm6
(m × 20H) + 80FH
M_DATAm7
(m × 20H) + 810H
M_IDLm
(m × 20H) + 812H
M_IDHm
(m × 20H) + 814H
M_CONFm
(m × 20H) + 815H
M_STATm
(m × 20H) + 816H
SC_STATm
(m × 20H) + 818H
to –
(m × 20H) + 81FH
Notes: 1. m = number of CAN message buffer (m = 00 to 31)
2. The address of a message buffer entry is calculated according to the following formula:
effective address = PP_BASE + address offset
3. The V850E/CA2 Jupiter device does not contain an event processor. Therefore the mes-
sage event bytes are reserved.
However, these registers can be used for storing user data in case that the event processing
is disabled explicitly by clearing the bit EVM in the register "CAN global status register" and
by clearing the bit ERQ in the "Message status register".
Chapter 14 FCAN Interface Function

Table 14-2: CAN Message Buffer Registers Layout

Note 1
Message event register 0
Message event register 1
Message event register 2
Message event register 3
Message data length code register
Message control register
Message time stamp register
Message data byte 0
Message data byte 1
Message data byte 2
Message data byte 3
Message data byte 4
Message data byte 5
Message data byte 6
Message data byte 7
Message identifier register
(lower half-word)
Message identifier register
(upper half-word)
Message configuration register
Message status register
Message set/clear status register
Reserved
Preliminary User's Manual U15839EE1V0UM00
Ref.
Name
Page
Note 3
Note 3
Note 3
Note 3
Access Type
R/W 1 bit 8 bit
×
R/W
484
×
R/W
– –
×
484 R/W
×
480 R/W
×
481 R/W
483 R/W
×
R/W
×
R/W
×
R/W
×
R/W
478
×
R/W
×
R/W
×
R/W
×
R/W
R/W
472
R/W
×
473 R/W
×
475 R
477 W
– –
16 bits
×
×
×
×
431