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(2)
Timer Dn compare register (CMDn) (n = 0, 1)
CMDn and the TMDn registers' count value are compared, and an interrupt request signal
(INTTMDn) is generated when a match occurs. TMDn is cleared, synchronized with this match. If
the CAE bit of the TMCDn register is set to "0", a reset is performed asynchronously, and the
registers are initialized (n = 0, 1).
The CMDn register is configured with a master/slave configuration. When a write operation to a
CMDn register is performed, data is first written to the master register and then the master
register's data is transferred to the slave register. In a compare operation, the slave register's value
is compared with the count value of the TMDn register. When a read operation to a CMDn register
is performed, data in the master side is read out.
CMDn can be read/written in 16-bit units.
Figure 10-20: Timer Dn Compare Register (CMDn) (n = 0, 1)
15
14
13
CMD0
CMD1
Cautions: 1. A write operation to the a CMDn register requires f
that was set in the CMDn register is transferred to internal units. When writing
continuously to the CMDn register, be sure to reserve a time interval of at least
f
/2 clocks.
PCLK
2. The CMDn register can be overwritten only once in a single TMDn register cycle
(from 0000H until an INTTMDn interrupt is generated due to a match of the TMDn
register and CMDn register). If this cannot be secured by the application, make
sure that the CMDn register is not overwritten during timer operation.
3. Note that an INTTMDn interrupt will be generated after an overflow if a value less
than the counter value is written in the CMDn register during TMDn register
operation (Figure 10-21, "Timing of Timer Dn Operation," on page 300).
Chapter 10 Timer
12
11
10
9
8
Preliminary User's Manual U15839EE1V0UM00
7
6
5
4
3
2
1
0
Address
FFFF F542H 0000H
FFFF F552H 0000H
/2 clocks until the value
PCLK
Initial
value
299
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