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(2)
Generation of exception in service program
Service program of maskable interrupt or exception
...
...
• EIPC saved to memory or register
• EIPSW saved to memory or register
...
• TRAP instruction
...
• Saved value restored to EIPSW
• Saved value restored to EIPC
• RETI instruction
The priority order for multiple interrupt processing control has 8 levels, from 0 to 7 for each maska-
ble interrupt request (0 is the highest priority), but it can be set as desired via software. Setting of
the priority order level is done using the PPRn0 to PPRn2 bits of the interrupt control request reg-
ister (PlCn), which is provided for each maskable interrupt request. After system reset, an interrupt
request is masked by the PMKn bit and the priority order is set to level 7 by the PPRn0 to PPRn2
bits.
The priority order of maskable interrupts is as follows.
(High)
Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7
Interrupt processing that has been suspended as a result of multiple processing control is
resumed after the processing of the higher priority interrupt has been completed and the RETI
instruction has been executed.
A pending interrupt request is acknowledged after the current interrupt processing has been com-
pleted and the RETI instruction has been executed.
Caution:
In a non-maskable interrupt processing routine (time until the RETI instruction is exe-
cuted), maskable interrupts are suspended and not acknowledged.
Chapter 8 Interrupt/Exception Processing Function
Preliminary User's Manual U15839EE1V0UM00
¨ Exception such as TRAP instruction acknowledged.
(Low)
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