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6.6 Operating Precautions
(1)
Operation on Reset:
At the time of a reset, tags are automatically cleared (invalidated), which puts the next data
replacement in a state of being performed from way 0. Therefore, if there is an access to the
instruction cache within a period of as many clock cycles as the number of lines after a reset, the
CPU stops until the tags are cleared (become valid).
(2)
Setting registers:
Be sure to set the registers shown below running the code from an uncacheable area. However,
set bit 4 of the instruction cache control register (ICC) using a cacheable area.
• Chip area select control registers (CSC0, CSC1)
• Peripheral I/O area select control register (BPC)
• Bus size configuration register (BSC)
• Endian configuration register (BEC)
• Cache configuration register (BHC)
• Instruction cache control register (ICC
• Instruction cache data configuration register (ICD)
Note: Excluding bit 4
(3)
Initial program settings:
Always execute the following instruction before setting the cache configuration register BHC with
the initial settings of the user program immediately following system reset.
st.h r0, 0xfffff072[r0]
Following execution of this instruction, the cache is enabled by setting "cache enable"
(BHn0 bit = "1") as the instruction cache setting with the BHC register (n = 7 to 0).
(4)
Setting BHC register:
In the case of CSn areas for which an instruction to set the BHC register exists in the same CSn
area, cache enable/disable settings for the instruction cache using this instruction cannot be per-
formed (n = 7 to 0). Instruction cache enable/disable settings are possible only for those CSn
areas in which no instruction for setting the BHC register exists.
For example, if a BHC register setting instruction exists in the CS0 area, the instruction cache of
the CS0 area cannot be set (cache enable/disable settings). In this case, only the instruction
cache settings for areas CS1 to CS7 are possible.
Chapter 6 Instruction Cache
Preliminary User's Manual U15839EE1V0UM00
Note
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