Cache Configuration - NEC V850E/CA2 JUPITER Preliminary User's Manual

4.7 Cache Configuration

The cache configuration register (BHC) is used to set the cache memory configuration for each CS
area selected by the chip select signals (CS0 to CS7).
(1) Cache configuration register (BHC)
This register can be read or written in 16-bit units.
15 14 13 12
BEC 0 BH70 0 BH60
CS7 CS6
Bit Position Bit Name
14, 12, 10, 8, BHn0
6, 4, 2, 0 (n = 0 to 7)
Cautions: 1. Be sure to disable the cache for big endian format CS area and CS areas set as
the following areas.
• ROM area
• RAM area
• Peripheral I/O area
• Programmable peripheral I/O area
2. The bits marked as 0 are reserved. They have to leave to 0
Note: n = 0 to 7
118
Chapter 4 Bus Control Function
11 10 9 8 7
0 BH50 0 BH40 0
CS5 CS4 CS3
Sets whether or not the instruction cache located in the block n area can be
used.
BHn0
0 Cache not available
1 Cache available
Preliminary User's Manual U15839EE1V0UM00
6 5 4 3 2
BH30 0 BH20 0 BH10
CS2 CS1
Function
Instruction Cache Setting
Initial
1 0 Address
value
0 BH00 FFFFF06AH 0000H
CS0