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8.7 Multiple Interrupt Processing Control
Multiple interrupt processing control is a process by which an interrupt request that is currently being
processed can be interrupted during processing if there is an interrupt request with a higher priority
level, and the higher priority interrupt request is received and processed first.
If there is an interrupt request with a lower priority level than the interrupt request currently being proc-
essed, that interrupt request is held pending.
Maskable interrupt multiple processing control is executed when an interrupt has an enable status (ID =
0). Thus, if multiple interrupts are executed, it is necessary to have an interrupt enable status (ID = 0)
even for an interrupt processing routine.
If a maskable interrupt enable or a software exception is generated in a maskable interrupt or software
exception service program, it is necessary to save EIPC and EIPSW.
This is accomplished by the following procedure.
(1)
Acknowledgment of maskable interrupts in service program
Service program of maskable interrupt or exception
...
...
• EIPC saved to memory or register
• EIPSW saved to memory or register
• EI instruction (interrupt acknowledgment enabled)
...
...
...
...
• DI instruction (interrupt acknowledgment disabled)
• Saved value restored to EIPSW
• Saved value restored to EIPC
• RETI instruction
234
Chapter 8 Interrupt/Exception Processing Function
Preliminary User's Manual U15839EE1V0UM00
¨ Maskable interrupt acknowledgment
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