Single-Step Transfer Mode; Figure 7-20: Single-Step Transfer Example 1; Figure 7-21: Single-Step Transfer Example 2 - NEC V850E/CA2 JUPITER Preliminary User's Manual

7.5.2 Single-step transfer mode

In single-step transfer mode, the DMAC releases the bus at each byte/halfword/word transfer. Once a
DMA transfer request signal is received, transfer is performed again. This operation continues until a
terminal count occurs.
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the
higher priority DMA request always takes precedence.
Figure 7-20, "Single-Step Transfer Example 1," on page 189 shows a DMA transfer example in single-
step transfer mode.
DMA Transfer
Request CH1
CPU CPU
Figure 7-21, "Single-Step Transfer Example 2," on page 189 shows a DMA transfer example in single-
step transfer mode in which a higher priority DMA transfer request is generated while the lower DMA
channel has released the bus.
DMA Transfer
Request CH0
DMA Transfer
Request CH1
CPU CPU
Note: The bus is always released
Chapter 7 DMA Functions (DMA Controller)

Figure 7-20: Single-Step Transfer Example 1

Note Note
CPU DMA1 CPU DMA1

Figure 7-21: Single-Step Transfer Example 2

Note Note
CPU DMA1 CPU DMA1 CPU
Preliminary User's Manual U15839EE1V0UM00
Note
CPU DMA1 CPU DMA1 CPU
DMA channel 1
terminal count
Note Note
DMA0 CPU DMA0 CPU
CPU CPU CPU CPU
Note Note
DMA0 CPU DMA1 CPU
DMA channel 0 DMA channel 1
terminal count terminal count
CPU CPU
DMA1 CPU
189