NEC V850E/CA2 JUPITER Preliminary User's Manual page 16

Figure 10-53: Timing of PWM operation (match and clear) ............................................................. 341
Figure 10-54: Timing when 0000H is set in GCCnm (match and clear) .......................................... 342
Figure 10-55: Timing when the same value as set in GCCn0/GCCn5 is set in GCCnm
(match and clear)....................................................................................................... 343
Figure 10-56: Timing when the value of GCCnm exceeding GCCn0 or GCCn5
(match and clear)....................................................................................................... 344
Figure 10-57: Timing when GCCnm is rewritten during operation (match and clear)...................... 345
Figure 10-58: Timing of Edge detection noise elimination ............................................................... 346
Figure 11-1: Block Diagram of Watch Timer.................................................................................. 349
Figure 11-2: Watch Timer Mode Control Register (WTM) (1/2)..................................................... 350
Figure 11-3: Operation Timing of Watch Timer/Interval Timer....................................................... 355
Figure 12-1: Block Diagram of Watchdog Timer............................................................................ 357
Figure 12-2: Watchdog Timer Clock Selection Register (WDCS).................................................. 359
Figure 12-3: Watchdog Timer Mode Register (WDTM) ................................................................ 360
Figure 12-4: Watchdog Timer Mode Register (WCMD) ................................................................ 361
Figure 12-5: Watchdog Timer Mode Register (WPHS) ................................................................. 361
Figure 13-1: Asynchronous Serial Interfaces Block Diagram ........................................................ 366
Figure 13-2: Asynchronous Serial Interface Mode Registers (ASIM0, ASIM1) (1/3) ..................... 367
Figure 13-3: Asynchronous Serial Interface Status Registers (ASIS0, ASIS1) ............................. 370
Figure 13-4: Asynchronous Serial Interface Transmit Status Registers (ASIF0, ASIF1)............... 371
Figure 13-5: Reception Buffer Registers (RXB0, RXB1) ............................................................... 372
Figure 13-6: Transmission Buffer Registers (TXB0, TXB1) ........................................................... 373
Figure 13-7: Asynchronous Serial Interface Transmit/Receive Data Format................................. 375
Figure 13-8: Asynchronous Serial Interface Transmission Completion Interrupt Timing............... 376
Figure 13-9: Continuous Transmission Starting Procedure ........................................................... 378
Figure 13-10: Continuous Transmission End Procedure ................................................................. 379
Figure 13-11: Asynchronous Serial Interface Reception Completion Interrupt Timing .................... 380
Figure 13-12: When Reception Error Interrupt Is Separated from INTSRn Interrupt
(ISRM Bit = 0)............................................................................................................ 381
Figure 13-13: When Reception Error Interrupt Is Included in INTSRn Interrupt
(ISRM Bit = 1)............................................................................................................ 381
Figure 13-14: Noise Filter Circuit ..................................................................................................... 383
Figure 13-15: Timing of RXD5n Signal Judged as Noise ................................................................ 383
Figure 13-16: Baud Rate Generator (BRG) Configuration of UART5n (n = 0, 1) ............................ 384
Figure 13-17: Clock Select Registers (CHKSR0, CHKSR1)............................................................ 385
Figure 13-18: Baud Rate Generator Control Registers (BRGC0, BRGC1) ..................................... 386
Figure 13-19: Allowable Baud Rate Range During Reception......................................................... 389
Figure 13-20: Transfer Rate During Continuous Transmission ....................................................... 391
Figure 13-21: Block Diagram of Clocked Serial Interfaces .............................................................. 394
Figure 13-22: Clocked Serial Interface Mode Registers (CSIM0 to CSIM2).................................... 395
Figure 13-23: Clocked Serial Interface Clock Selection Registers (CSIC0 to CSIC2) (1/2) ............ 396
Figure 13-24: Clocked Serial Interface Reception Buffer Registers (SIRB0 to SIRB2) ................... 398
Figure 13-25: Clocked Serial Interface Reception Buffer Registers Low (SIRBL0 to SIRBL2)........ 399
Figure 13-26: Clocked Serial Interface Read-Only Reception Buffer Registers
(SIRBE0 to SIRBE2).................................................................................................. 400
Figure 13-27: Clocked Serial Interface Read-Only Reception Buffer Registers Low
(SIRBEL0 to SIRBEL1).............................................................................................. 401
Figure 13-28: Clocked Serial Interface Transmission Buffer Registers (SOTB0 to SOTB2) ........... 402
Figure 13-29: Clocked Serial Interface Transmission Buffer Registers Low
(SOTBL0 to SOTBL2)................................................................................................ 403
Figure 13-30: Clocked Serial Interface Initial Transmission Buffer Registers
(SOTBF0 to SOTBF2) ............................................................................................... 404
Figure 13-31: Clocked Serial Interface Initial Transmission Buffer Registers Low
(SOTBFL0 to SOTBFL2) ........................................................................................... 405
Figure 13-32: Serial I/O Shift Registers (SIO0 to SIO2) .................................................................. 406
Figure 13-33: Serial I/O Shift Registers Low (SIOL0 to SIOL2)....................................................... 407
Figure 13-34: Timing Chart in single Transfer Mode (1/2) ............................................................... 409
Figure 13-35: Timing Chart According to Clock Phase Selection (1/2)............................................ 411
16
Preliminary User's Manual U15839EE1V0UM00