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Chapter 9 Clock Generator
(2)
When released by Watchdog Timer RESET input
CPU operation starts after main oscillation stabilization time has been secured
Figure 9-14: STOP mode release by Watchdog reset, NMI, INT
STOP mode setting
Main Oscillation circuit
System clock
STOP state
NMI or INT input
Oscillation stabilization counter
Oscillation circuit stop
count time
After oscillation stabilization time has passed, CPU starts operation.
Before entering the STOP mode the SSCG and PLL are switched off by hardware. After the STOP
mode has been released the SSCG and PLL can be switched on any software again once.
However, the start-up of the SSCG and PLL cause always a certain delay of some Milliseconds.
During this time, the clock operates, but the CPU operation is suspended due to clock security
reasons.
If it is required to have a fast response when waking up from STOP mode, the SSCG and PLL
should not be re-enabled after waking up, as this causes again the delay. In this case,
time-relevant reactions of the CPU should be done first, before re-enabling the PLL.
Preliminary User's Manual U15839EE1V0UM00
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