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10.3.4 Control registers
(1)
Timer Gn Mode Register (TMGMn) (n = 0, 1)
This register can be read/written in 16-bit, 8-bit or 1-bit units.
15
14
13
12
TMGM0 POWER OLDE CSE12 CSE11 CSE10 CSE02 CSE01 CSE00 CCSG5 CCSG0
TMGM1 POWER OLDE CSE12 CSE11 CSE10 CSE02 CSE01 CSE00 CCSG5 CCSG0
Bit Position
Bit Name
15
POWER
14
OLDE
CSEx2,
13 to 8
CSEx1,
CSEx0
Chapter 10 Timer
Figure 10-30: Timer Gn Mode Register (TMGMn) (1/2)
11
10
9
8
Timer Gn Operation control.
0: operation Stop
the capture registers and TMGSTn register are cleared
the TOGnm pins (m = 1 to 4) are inactive all the time
1: operation enable
Remark: At least 7 peripheral-clocks (f
Set Output Delay Operation.
0: Don't perform output delay operation
1: Set output delay to n count-clocks
Caution: When the POWER-Bit is set, the rewriting of this Bit is
prohibited! Simultaneously writing with the POWER bit is allowed.
Remark: The delay operation is used for EMI counter measures.
Selects internal count clock of TMG
CSEx2
CSEx1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Caution: When the POWER-Bit is set, the rewriting of this Bits are
prohibited! Simultaneously writing with the POWER bit is allowed.
Remarks: 1. x = 0, 1
2. f
: peripheral clock
PCLK
Preliminary User's Manual U15839EE1V0UM00
7
6
5
4
3
0
0
CLRG1 TMG1E CLRG0 TMG0E FFFF F640H
0
0
CLRG1 TMG1E CLRG0 TMG0E FFFF F680H
Function
) are need to start the timer function
PCLK
CSEx0
0
1
0
1
0
1
0
1
2
1
0
Address
Count Clock
f
PCLK
f
/2
PCLK
f
/4
PCLK
f
/8
PCLK
f
/16
PCLK
f
/32
PCLK
f
/64
PCLK
f
/128
PCLK
Initial
value
0000H
0000H
313
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