Configuration; Figure 9-1: Block Diagram Of The Clock Generator - NEC V850E/CA2 JUPITER Preliminary User's Manual

9.2 Configuration

STOP
WATCH/S-WATCH
f
Main System
X1
Clock OSC
X2
f
XT1
Subsystem
Clock OSC
XT2
This block diagram does not necessarily show the exact wiring in hardware but the functional structure.
240
Chapter 9 Clock Generator

Figure 9-1: Block Diagram of the Clock Generator

STOP
WATCH/S-WATCH
SSCG
64 (f = 4 MHz)
1/2
X
50 (f = 5 MHz)
X
STOP
WATCH/S-WATCH
PLL Circuit
X
8
XT
1/128
f
XXT
Preliminary User's Manual U15839EE1V0UM00
f /8
XX
f /6
XX
f
f
/4
XX
XX
f /3
XX
f
XXP
1/2
Prescaler
f /4 f /32
XXT XXT
WATCH/S-WATCH
IDLE
HALT
WATCH
IDLE
Watchdog Timer
f
WDT
Watch Timer
f
CKSEL2
Watch Timer
f
CKSEL1
CPU/BCU
f
CPU
Peripherals
f
PCLK