Figure 10-52: Timing When Gccnm Is Rewritten During Operation (Match And Clear) - NEC V850E/CA2 JUPITER Preliminary User's Manual

32-/16-bit romless microcontroller
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(f) When GCCnm (m = 1 to 4) is rewritten during operation (match and clear)
When the value of GCCn1 is changed from 0555H to 0AAAH, the operation described below is
performed.
TMGn0 is selected as the counter, and 0FFFH is set in GCCn0.

Figure 10-52: Timing when GCCnm is rewritten during operation (match and clear)

f
PCLK
ENFG0
TMGn0
GCCn1 Slave register
GCCn1 Master register
INTCCGn1
Caution:
To perform successive write access during operation, for rewriting the GCCny
register (n = 1 to 4), you have to wait for minimum 7 peripheral clocks periods (f
Chapter 10 Timer
Match
0555H
0555H
Preliminary User's Manual U15839EE1V0UM00
Reload in 5 clock periods
0AAAH
Match
0AAAH
).
PCLK
339

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