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(b) When the bus width is 8 bits (Little Endian)
<1> Access to address 4n
1-st Access
31
24
23
16
15
Address
8
7
7
4n
0
0
Word data
External
data bus
<2> Access to address 4n + 1
1-st Access
31
24
23
16
15
Address
8
7
7
4n + 1
0
0
Word data
External
data bus
Preliminary User's Manual U15839EE1V0UM00
Chapter 4 Bus Control Function
2-nd Access
31
24
23
16
15
Address
8
7
7
4n + 1
0
0
Word data
External
data bus
2-nd Access
31
24
23
16
15
Address
8
7
7
4n + 2
0
0
Word data
External
data bus
3-rd Access
31
24
23
16
15
Address
8
7
7
4n + 2
0
0
Word data
External
data bus
3-rd Access
31
24
23
16
15
Address
8
7
7
4n + 3
0
0
Word data
External
data bus
4-th Access
31
24
23
16
15
Address
8
7
7
4n + 3
0
0
Word data
External
data bus
4-th Access
31
24
23
16
15
Address
8
7
7
4n + 4
0
0
Word data
External
data bus
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