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1.6.1 On-chip units
(1)
CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits → 32 bits or 32 bits x 32
bits → 64 bits) and the barrel shifter (32 bits), help accelerate processing of complex instructions.
(2)
Bus control unit (BCU)
BCU starts a required external bus cycle based on the physical address obtained by the CPU.
When an instruction is fetched from external memory area and the CPU does not send a bus cycle
start request, the BCU generates a prefetch address and prefetches the instruction code. The
prefetched instruction code is stored in an instruction queue in the CPU.
The BCU provides a page ROM controller (ROMC) and a DMA controller (DMAC).
(a) Page ROM controller (ROMC)
This controller supports accessing ROM that includes the page access function.
It performs address comparisons with the immediately preceding bus cycle and executes wait con-
trol for normal access (off page)/page access (on page). It can handle page widths of 8 to 128
bytes.
(b) DMA controller (DMAC)
Instead of the CPU, this controller controls data transfer between memory and I/O.
There is one address mode: 2-cycle transfer and there are three bus modes: single transfer, single
step transfer, and block transfer.
(3)
ROM
The µPD703128, µPD703129 is a ROM-less MCU containing a 16-bit wide non-multiplexed bus
interface to be able to fetch instructions/data from external memories.
(4)
RAM
RAM are mapped from address FFFF8000H.
During instruction fetch, data can be accessed from the CPU in 1-clock cycles.
(5)
Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP5) from on-chip periph-
eral I/O and external hardware. Eight levels of interrupt priorities can be specified for these inter-
rupt requests, and multiple-interrupt servicing control can be performed for interrupt sources.
(6)
Spread spectrum Clock generator (SSCG)
The spread spectrum clock generator (SSCG) generates a spread spectrum system clock for the
CPU/BCU system based on the main-oscillator input clock. Four types of clocks are generated
(f
/8, f
/6, f
/4, f
XX
XX
XX
(7)
Clock generator (CG)
The clock generator includes two types of oscillators (Main-OSC and Sub-OSC). The Peripheral
PLL can also be used as the clock supply for the CPU/BCU (f
The peripherals can be supplied with the clock f
30
Chapter 1 Introduction
/3), and can be supplied as the operating clock for the CPU/BCU (f
XX
Preliminary User's Manual U15839EE1V0UM00
, f
XXP
XXP
or f
/2.
XXP
XXP
CPU
/2).
).
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