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3.6.4 Internal peripheral function wait control register (VSWC)
This register inserts wait states to the internal access of peripheral SFRs.
This register can be read or written in 1-bit and 8-bit units.
Figure 3-20: Internal peripheral function wait control register (VSWC) Format
7
6
VSWC
0
SUWL2 SUWL1 SUWL0
0
1
Bit Name
SUWL2,
SUWL1,
SUWL0
VSWL2,
VSWL1,
VSWL0
Caution:
With respect to the specified operation frequency the following register settings for
VSWC are recommended.
Chapter 3 CPU Function
5
4
3
0
1
1
0
Setup wait for internal peripheral bus length
SUWL2
SUWL1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Internal peripheral bus wait length
VSWL2
VSWL1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Preliminary User's Manual U15839EE1V0UM00
2
1
VSWL2 VSWL1 VSWL0 FFFFF06EH R/W
1
1
Description
SUWL0
Number of data wait states (n = 7 - 0)
0
1
1 system clock
0
2 system clock
1
3 system clock
0
4 system clock
1
5 system clock
0
6 system clock
1
7 system clock (default)
VSWL0
Number of data wait states (n = 7 - 0)
0
1
1 system clock
0
2 system clock
1
3 system clock
0
4 system clock
1
5 system clock
0
6 system clock
1
7 system clock (default)
0
Address
R/W
1
0
0
Reset
Value
77H
107
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