NEC V850E/CA2 JUPITER Preliminary User's Manual page 15

Figure 9-11: Sub Watch mode released by RESET input ............................................................. 263
Figure 9-12: Sub Watch mode release by Watchdog reset, NMI, INT........................................... 264
Figure 9-13: STOP mode released by RESET input ..................................................................... 266
Figure 9-14: STOP mode release by Watchdog reset, NMI, INT................................................... 267
Figure 9-15: Power Save Control Register (PSC) ........................................................................ 268
Figure 9-16: Power Save Mode Register (PSM) .......................................................................... 270
Figure 10-1: Block Diagram of Timer C ......................................................................................... 273
Figure 10-2: Timer C counter (TMC0) .......................................................................................... 274
Figure 10-3: Capture/Compare Register 0 (CCC00) ..................................................................... 276
Figure 10-4: Capture/Compare Register 1 (CCC01) ..................................................................... 276
Figure 10-5: Timer C control Register 0 (TMCC00) (1/2) ............................................................. 278
Figure 10-6: Timer C control Register 1 (TMCC01) (1/2) ............................................................. 280
Figure 10-7: Valid Edge Selection Register (SESC0).................................................................... 282
Figure 10-8: Timing of basic operation of Timer C ........................................................................ 283
Figure 10-9: Timing of interrupt operation after overflow ............................................................... 284
Figure 10-10: Timing of capture for pulse cycle measurement (rising edge)................................... 285
Figure 10-11: Timing of capture for pulse width measurement (both edges) .................................. 286
Figure 10-12: Timing of cycle measurement operation ................................................................... 288
Figure 10-13: Timing of compare operation..................................................................................... 289
Figure 10-14: Timing of interval timer operation .............................................................................. 290
Figure 10-15: Timing of PWM output operation (overview) ............................................................. 291
Figure 10-16: Timing of PWM output operation (detail) ................................................................... 292
Figure 10-17: Multiplexed Inputs for Timer C Sub Oscillator Calibration Function .......................... 294
Figure 10-18: Block Diagram of Timer Dn (n = 0, 1) ........................................................................ 296
Figure 10-19: Timer Dn counter register (TMDn) (n = 0, 1) ........................................................... 298
Figure 10-20: Timer Dn Compare Register (CMDn) (n = 0, 1) ........................................................ 299
Figure 10-21: Timing of Timer Dn Operation ................................................................................... 300
Figure 10-22: Timer Dn Control Register (TMCDn) (n = 0, 1) ........................................................ 301
Figure 10-23: Timing of Compare Operation (1/2)........................................................................... 302
Figure 10-24: Block Diagram of Timer Gn ....................................................................................... 308
Figure 10-25: Timer Gn Counter 0 Value Registers TMGn0 ........................................................... 310
Figure 10-26: Timer Gn Counter 1 Value Registers TMGn1 ........................................................... 310
Figure 10-27: Timer Gn counter TMGn0 assigned Capture/Compare Register (GCCn0)............... 311
Figure 10-28: Timer Gn counter TMGn1 assigned Capture/Compare Register (GCCn5)............... 311
Figure 10-29: Timer Gn free assignable Capture/Compare Registers (GCCnm) (m = 1 to 4) ........ 312
Figure 10-30: Timer Gn Mode Register (TMGMn) (1/2)
Figure 10-31: Timer Gn Mode Register Low (TMGMnL) ............................................................... 315
Figure 10-32: Timer Gn Mode Register Low (TMGMnH) ............................................................... 315
Figure 10-33: Timer Gn Channel Mode Register (TMGCMn).......................................................... 316
Figure 10-34: Timer Gn Channel Mode Register (TMGCMnL)........................................................ 317
Figure 10-35: Timer Gn Channel Mode Register (TMGCMnH) ....................................................... 317
Figure 10-36: Timer Gn Output Control Register (OCTLGn) ........................................................... 318
Figure 10-37: Timer Gn Output Control Register Low (OCTLGnL) ................................................. 319
Figure 10-38: Timer Gn Output Control Register High (OCTLGnH) ................................................ 319
Figure 10-39: Timer Gn Status Register (TMGSTn) ........................................................................ 320
Figure 10-40: Timing of Output delay operation .............................................................................. 321
Figure 10-41: Timing when both edges of TIGn0 are valid (free run) .............................................. 326
Figure 10-42: Timing of capture trigger edge detection (free run) ................................................... 327
Figure 10-43: Timing of starting capture trigger edge detection ...................................................... 328
Figure 10-44: Timing of compare mode (free run) ........................................................................... 329
Figure 10-45: Timing when GCCn1 is rewritten during operation (free run) .................................... 330
Figure 10-46: Timing of PWM operation (free run) .......................................................................... 332
Figure 10-47: Timing when 0000H is set in GCCnm (free run)........................................................ 333
Figure 10-48: Timing when FFFFH is set in GCCnm (free run)....................................................... 333
Figure 10-49: Timing when GCCnm is rewritten during operation (free run) ................................... 334
Figure 10-50: Timing when both edges of TIGm are valid (match and clear).................................. 336
Figure 10-51: Timing of compare operation (match and clear)........................................................ 338
Figure 10-52: Timing when GCCnm is rewritten during operation (match and clear)...................... 339
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