Figure 10-43: Timing Of Starting Capture Trigger Edge Detection - NEC V850E/CA2 JUPITER Preliminary User's Manual

(c) Timing of starting capture trigger edge detection
A capture trigger input signal (TIGny) is synchronized in the noise eliminator for internal use.
Edge detection starts when 1 count clock period (f
operation starts. (This is because masking is performed to prevent the initial TIGny level from
being recognized as an edge by mistake.). The timing chart for starting edge detection is shown
below.
Basic settings (x= 0, 1 and y = 0 to 5):

Figure 10-43: Timing of starting capture trigger edge detection

f
PCLK
f
COUNTx
TMG0E(TMG1E)
ENFG0(ENFG1)
count_up0(count_up1)
TMGn0/TMGn1
TIGny
INTCCGny
GCCny
328
Chapter 10 Timer
Bit Value
CSEx2 0
CSEx1 1
CSEx0 0
IEGy1 1
IEGy0 1
Invalid edge input
0001H
Preliminary User's Manual U15839EE1V0UM00
) has been input after timer count
COUNT
Remark
Count clock = f
PCLK
detection of both edges
Edge detection start
0002H 0003H 0004H
/4
0005H 0006H
0005H