Table of Contents
Advertisement
(3)
Operation on Instruction Cache Miss
(1)
On a fetch access from memory, the CPU outputs the instruction fetch request and the
concerned address to the instruction cache.
(2)
If an instruction cache miss occurs due to the address not existing in the instruction cache,
the fetch request and the address will be output from the instruction cache to the BCU.
(3)
The BCU then outputs the address to external memory via the VSB and refills the
instruction cache with one line (4 words) at the address to be read.
(4)
The instruction cache then transfers the data to be read among the 4 words of refill data to
the CPU.
Caution:
The miss penalty time when a miss occurs varies depending on such things as mem-
ory controller specifications for external memory and VSB bus cycle wait insertion
time.
(1)
(4)
CPU
NB85E
Chapter 6 Instruction Cache
Figure 6-7: Operation on Instruction Cache Miss
Instruction Cache
Instruction
Cache Interface
(3)
BCU
Preliminary User's Manual U15839EE1V0UM00
(2)
(3)
VSB
External Memory
(3)
MEMC
161
Advertisement
Table of Contents
