Table of Contents
Advertisement
(2)
Compare operation (match and clear)
Basic settings (m = 1 to 4):
(a) Example: Interval timer (match and clear)
Setting Method
(1)
An usable compare register is one of GCCn1 to GCCn4, and the corresponding counter must be
selected with the TBGm bit.
(2)
Select a count clock cycle with the CSE12 to CSE10 bits (TMGn1) or CSE02 to CSE00 bits
(TMGn0).
(3)
Set an upper limit on the value of the counter in GCCn0 or GCCn5.
(4)
Write data to GCCnm.
(5)
Start timer operation by setting the POWER bit and TMGxE bit (x = 0, 1).
Operation:
(1)
When the value of the counter matches the value of GCCnm, a match interrupt (INTCCGnm) is
output.
(2)
When the value of GCCn0 or GCCn5 matches the value of the counter, INTCCGn0 (or
INTCCGn5) is output, and the counter is cleared. This operation is referred to as "match and
clear".
(3)
The counter resumes count-up operation starting with 0000H.
Chapter 10 Timer
Bit
CCSG0n
CCSG5n
SWFGm
CCSGm
TBGm
Preliminary User's Manual U15839EE1V0UM00
Value
Remark
1
match and
clear mode
1
0
disable TOGnm
Compare mode
1
for GCCnm
assign counter
for GCCnm
X
0: TMGn0
1: TMGn1
337
Advertisement
Table of Contents
