Figure 10-50: Timing When Both Edges Of Tigm Are Valid (Match And Clear) - NEC V850E/CA2 JUPITER Preliminary User's Manual

(b) Example: Capture where both edges of TIGm are valid (match and clear)
For the timing chart TMGn0 is selected as the counter corresponding to TOGn1, and 0FFFH is set
in GCCn0.

Figure 10-50: Timing when both edges of TIGm are valid (match and clear)

f
PCLK
t
f
COUNTx
TMGn0 0000H 0001H
Count start
TIGn1
GCCn1
INTCCGn1
INTCCGn0
CCFG1
Remark: The figure above shows an image. In actual circuitry, 3 to 4 periods of the count-up signal
(f ) are required from the input of a waveform to TOGn1 until a capture interrupt is
COUNT
output. (See Figure 10-42, "Timing of capture trigger edge detection (free run)," on page
327.)
Caution: If two or more match and clear events occur between captures, a software-based
measure needs to be taken to count INTCCGn0 or INTCCGn5.
(c) When 0000H is set in GCCn0 or GCCn5 (match and clear)
When 0000H is set in GCCn0 (GCCn5), the value of the counter is fixed at 0000H, and does not
operate. Moreover, INTCCGn0 (INTCCGn5) continues to be active.
(d) When FFFFH is set in GCCn0 or GCCn5 (match and clear)
When FFFFH is set in GCCn0 (GCCn5), operation equivalent to the free-run mode is performed.
When an overflow occurs, INTTMGn0 (INTTMGn1) is generated, but INTCCGn0 (INTCCGn5) is
not generated.
336
Chapter 10 Timer
D0 D1
D0
No "match and clear"
Preliminary User's Manual U15839EE1V0UM00
0FFFH 0000H D2
Clear
D1
"Match and clear"
D3
D2 D3
No "match and clear"