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13.2.3 Control registers
(1)
Asynchronous serial interface mode registers (ASIM0, ASIM1)
The ASIMn register is an 8-bit register that controls the UART5n transfer operation.
This register can be read/written in 8 bit or 1-bit units (n = 0, 1).
Figure 13-2: Asynchronous Serial Interface Mode Registers (ASIM0, ASIM1) (1/3)
7
6
ASIM0
Power
TXE
ASIM1
Power
TXE
Bit Position
Bit Name
7
Power
6
TXE
Chapter 13 Serial Interface Function
5
4
RXE
PS1
RXE
PS1
Enables/disables clock operation.
0: Disable clock operation (reset internal circuit asynchronously.)
1: Enable clock operation
UART5n operation clock control and asynchronous reset of the internal
circuit are performed with the Power bit. When the Power bit is set to 0, the UART5n
operation clock stops (fixed to low level), and an asynchronous reset is applied to
internal UART5n latch.
The TXDn pin output is low level when the Power bit = 0, and high level when the
Power bit = 1. Therefore, perform Power setting in combination with port mode regis-
ter (PM1, PM2, PM6) so as to avoid malfunction on the other side at start-up (Set the
port to the output mode after setting the Power bit to 1).
Input from the RXDn pin is fixed to high level with Power bit = 0.
Enables/disables transfer.
0: Disable transfer (Perform synchronized reset of transfer circuit.)
1: Enable transfer
Cautions: 1. Set the TXE bit to 1 after setting the Power bit to 1 when starting
transfer. Set the Power bit to 0 after setting the TXE bit to 0 when
stopping transfer.
2. To initialize the transfer unit, clear (0) the TXE bit, and after
letting 2 Clock cycles (base clock) elapse, set (1) the TXE bit
again. If the TXE bit is not set again, initialization may not be
successful. (For details about the base clock, refer to 13.2.6
"Dedicated baud rate generators (BRG) of UART5n (n = 0, 1)" on
page 384.)
Preliminary User's Manual U15839EE1V0UM00
3
2
1
PS0
CL
SL
PS0
CL
SL
Function
0
Address
ISRM
FFFF FA00H
ISRM
FFFF FA40H
Initial
value
01H
01H
367
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