NEC V850E/CA2 JUPITER Preliminary User's Manual page 598

Instruction Mne-
Group monic
bit#3,
NOT1
disp16 [reg1]
Bit manip-
ulate
bit#3,
TST1
disp16 [reg1]
LDSR reg2, regID
STSR regID, reg2
TRAP vector
Special
RETI
HALT
Notes: 1. ddddddd is the higher 7 bits of disp8.
2. dddddd is the higher 6 bits of disp8.
3. ddddddddddddddd is the higher 15 bits of disp16.
4. Only the lower half-word data is valid.
5. ddddddddddddddddddddd is the higher 21 bits of dip22.
6. dddddddd is the higher 8 bits of disp9.
7. The op code of this instruction uses the field of reg1 through the source register is shown as reg2 in the
above table. Therefore, the meaning of register specification for mnemonic description and op code is
different from that of the other instructions
rrr = regID specification
RRRRR = reg2 specification
598
Appendix A
Table A-6: Instruction Set List (6/7)
Operand Opcode
01bbb1111
10RRRRR
ddddddddd
ddddddd
11bbb1111
10RRRRR
ddddddddd
ddddddd
rrrrr1111
11RRRRR
000000000
0100000
Note 7
rrrrr1111
11RRRRR
000000000
1000000
000001111
11iiiii
000000010
0000000
000001111
1100000
000000010
1000000
000001111
1100000
000000010
0100000
Preliminary User's Manual U15839EE1V0UM00
List of Instruction Sets
Operation
adr ← GR [reg1] + sign-extend
(disp16)
Z flag ← Not (Load-memory-bit
(adr, bit#3))
Store-memory-bit (adr, bit#3, Z
flag)
adr ← GR [reg1] + sign-extend
(disp16)
Z flag ← Not (Load-memory-bit
(adr, bit#3))
SR [regID] ←GR [reg2]
regID = EIPSW, FEPSW
regID = PSW
GR [reg2] ← SR [regID]
EIPC ← PC + 4 (Restored PC)
EIPSW ← PSW
ECR.EICC ← Interrupt code
PSW.EP ← 1
PSW.ID ← 1
PC ← 00000040H (vector = 00H
to 0FH)
00000050H (vector = 10H to
1FH)
if PSW.EP = 1
then PC ← EIPC
PSW ← EIPSW
else
if PSW.NP = 1
then PC ← FEPC
PSW ← FEPSW
else PC ← EIPC
PSW ← EIPSW
Stops
Flag
CY OV S Z SAT
×
×
× × × × ×
R R R R R