Sdram Controller - Toshiba TLCS-900/H1 Series Manual

(5) SDRAM controller

Symbol Name
Address
SDRAM
access
SDACR 0250H
control
register
SDRAM
Command
Interval
SDCISR 0251H
Setting
Register
SDRAM
refresh
SDRCR 0252H
control
register
SDRAM
SDCMM
command 0253H
register
SDRAM
HDRAM
SDBLS 0254H
burst length
register
7 6 5
−
SRDS SMUXW1 SMUXW0
R/W
1 0 0
Read Always Address multiplex
data shift write "0" type
function
00: Type A (A9- )
0: Disable
01: Type B (A10- )
1: Enable
10: Type C (A11- )
11: Reserved
STMRD STWR
1 1
TMRD TWR
0: 1 CLK 0: 1 CLK
1: 2 CLK 1: 2 CLK
−
R/W
0
Always
write "0"
SDBL5
0
For
HDMA5
HDMA burst length
0:1 Word Read / Single Write
1:Full Page Read / Burst Write
92CF30-602
4 3
SPRE
0 0
Read/Write
commands
0: Without
auto pre-
charge
1: With auto
precharge
STRP STRCD STRC2
R/W
1 1
TRP TRCD TRC
000: 1 CLK
0: 1 CLK 0: 1 CLK 001: 2 CLK
1: 2 CLK 1: 2 CLK 010: 3 CLK
011: 4 CLK
SSAE SRS2 SRS1
R/W
1 0
Self Refresh interval
Refresh 000: 47 states
auto
001: 78 states
exit
010: 156 states 110: 936 states
function
011: 312 states
0:Disable
1:Enable
SCMM2
Command issue
000: Don't care
001: Initialization sequence
a. Precharge All command
b. Eight Auto Refresh commands
c. Mode Register Set command
010: Precharge All command
100: Reserved
101: Self Refresh Entry command
110: Self Refresh Exit command
Others: Reserved
SDBL4 SDBL3 SDBL2
0 0
For For For
HDMA4 HDMA3 HDMA2
TMP92CF30
2 1 0
SMAC
R/W
0
SDRAM
controller
0: Disable
1: Enable
STRC1 STRC0
1 0 0
100: 5 CLK
101: 6 CLK
110: 7 CLK
111: 8 CLK
SRS0 SRC
0 0 0
Auto
100: 468 states Refresh
101: 624 states
0:Disable
111: 1248 states 1:Enable
SCMM1 SCMM0
R/W
0 0 0
SDBL1 SDBL0
0 0 0
For For
HDMA1 HDMA0
2009-06-12