Toshiba TLCS-900/H1 Series Manual page 419

Original cmos 32-bit microcontroller

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Table of Contents

(a) Single packet mode

This is data sequence of single packet mode when CPU bus interface is used.

Figure 3.16.13 is receiving sequence. Figure 3.16.14 is transmitting sequence.

This chapter focuses on access to FIFO. For Data sequence with USB host refer to

Endpoint 0 cannot be changed to exclusive single packet mode. Endpoints 1 to 3

can be changed between single packet and dual packet by setting Epx_SINGLE

Wait receiving data

DATASET register

• Check bit of EPx_DSET_A

SIZE register

RD receiving data of size in relevant

Figure 3.16.13 Receiving Sequence in Single Packet Mode

Receive valid data

DATASET register

• Set bit of EPx_D SET_A

• Assert EPx_DATASET signal

Interrupt by EPx_FULLA

Check DATASET register

• Size of SIZE_A_L confirmation

Size of SIZE_A_H confirmation

• Clear receiving data in FIFO

• Clear relevant bit of DATASET