Toshiba TLCS-900/H1 Series Manual page 153

3.8.2 Control Registers and Memory Access Operations After Reset
This section describes the registers to control the memory controller, their reset states and
the necessary settings after reset.
(1) Control Registers
The control registers of the memory controller are listed below.
･ Control registers: BnCSH/BnCSL(n = 0 to 3, EX)
Configures the basic settings of the memory controller, such as the memory type
specification and the number of wait states to be inserted into a read or write
cycle.
･ Memory Start Address register: MSARn(n = 0 to 3)
Specifies a start address fora selected address space.
･ Memory Address Mask register: MAMR (n = 0 to 3)
Specifies a block size for a selected address space.
･ Page ROM Control register: PMEMCR
Selects a method of accessing Page-ROM.
･Timing control registers: CSTMGCR, WRTMGCR, RDTMGCRn
Adjust the timing of rising and falling edges of control signals.
･ On-chip Boot ROM Control register: BROMCR
Selects a method of accessing Boot-ROM.
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TMP92CF30
2009-06-15