Toshiba TX79 Series Manuals

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Toshiba TX79 Series User Manual

Toshiba TX79 Series User Manual (309 pages)

TX System RISC Symmetric 2-way superscalar 64-bit CPU

Brand: Toshiba | Category: Microcontrollers | Size: 1.83 MB

Table of Contents

Table of Contents
3
Chapter 1. Introduction

44
- Other Terminology
  46
- Tx7901 Block
  50
Chapter 3. Configuration

50
Chapter 4. Address Maps

54
- Register Map
  55
- Table 4-1 List of 7901 Device
  56
Chapter 5. C790 Processor Core

66
- C790 Block
  67
Chapter 6. Sdram Memory Controller

72
Chapter 2 . Features

77
- Default Memory Map
  77
- R Egisters
  78
Chapter 11 . Interrupt Controller

79
Chapter 7. C790 Bus / G-Bus Bridge

99
- Figure 7-2 G-Bridge Address
  100
- A Ddress S Pace D Ecode and T Ranslation
  100
  - E Ndianness
    101
  - Figure 7-3 Bi-Endian Support
    101
  - Bu Error
    102
  - C790 Bus Statusr
    103
  - R Egisters
    103
  - Table 7-1 List of G-Bus Bridge
    103
  - C790 Bus Controlr
    104
  - Table 7-2 System Configuration
    104
  - C790 Bus Status Register
    106
  - C790 Bus Bad Address
    107
  - Cg Upper I/O Address
    107
  - Cg Lower Internal
    108
  - Cg Upper Rom a
    108
  - Cg Lower Rom a
    109
  - Cg Upper Pci a
    109
  - Cg Upper Lower
    110
  - Gc Upper Internal
    110
- CG Lower PCI Address Register (CGLPA0, CGLPA1, CGLPA2, CGLPA3)
  110
  - Gc Lower Internal
    111
  - Gc Upper Memory
    111
  - Gc Lower Memory
    112
  - Table 7-17 G-Bus Interrupts
    113
  - C790 Bus Latency
    114
- Interrupt Mask Register (IRMSK)
  114
  - Nmi Status Register
    115
- Table 7-21 G-Bus Masterl
  115
- Table 7-22 G-Bus Brokenm
  116
- Table 7-23 G-Bus Slave Latency
  116
- Table 7-24 G-Bridge Retryt
  117
- G-Bus Retry Timer
  117
- Table 7-25 the Gc Controlr
  118
- Table 7-26 G-Bridge Statusr
  119
- G-Bus Status Register
  119
- Table 7-28 G-Bus Arbiterr
  120
- G-Bus Bad Address Register
  120
- Table 7-29 G-Bus Arbitration
  121
- Table 7-30 G-Bus Arbiterg
  121
- Table 7-31 G-Bus Arbiterm
  122
- Table 7-32 G-Bus Arbiterg
  122
Chapter 8. Pci/G-Bus Bridge

123
- Figure 8-1 Top Level Blockd
  124
- Ignals
  125
- Table 8-1 Signal Description
  126
- PCI / G-Bus Bridge Interface Signals
  126
- T Heory of O Peration
  127
- Figure 8-3 Write to Pci from
  128
- G-Bus Master Reading from PCI (Bridge Master Read)
  128
- Figure 8-4 G-Bus Masterr
  130
- Figure 8-5 State Diagram for
  130
- Table 8-2 G-Bus Burst Sizes
  131
- PCI Master Writing to G-Bus Slave (Bridge Target Write)
  131
- PCI Master Reading from G-Bus Slave (Bridge Target Read)
  132
- Table 8-3 Supported Pci
  133
- Doorbell Feature
  133
- Figure 8-8 G-Bus to Pci Address
  134
- Lower Address Bits
  134
- PCI to G-Bus Address Mapping
  135
- Figure 8-10 Transactions with a
  136
- PCI Bus Arbiter
  137
- Reset
  138
- Retry Requests
  139
- PGB Memory Map
  140
- PGB G-Bus Registers
  142
  - R Egister D Ual -P Orting
    152
  - Table 8-17 Protection Levels
    152
  - PCI Core
    153
  - A Rchitecture
    154
- Figure 8-12 High Levela
  155
- Core
  155
- I/O Signals for PCI Core
  156
- Table 8-18 Enables from Pgb C
  157
- Table 8-19 Control and Data
  157
- Table 8-20 Control & Datas
  157
- Trdy_Timeout
  158
- Table 8-21 Configuration Pci
  159
- Table 8-22 Configuration Pci D
  159
- Table 8-23 Configuration Pci C
  159
- C Onfiguration R Egister D Escriptions
  159
- Table 8-24 Configuration Pci S
  160
- Table 8-25 Configurationd
  160
- Table 8-26 Configuration Class
  161
- Table 8-27 Configuration Cache
  161
- Table 8-28 Configurationm
  162
- Table 8-29 Header Type Register
  162
- Table 8-30 Subsystem Vendor
  162
- Table 8-31 Subsystem ID R
  163
- Table 8-32 Interrupt Liner
  163
- Table 8-33 Interrupt Pinr
  163
- Table 8-36 Configuration
  164
- MIN_GNT Register
  164
- Table 8-37 Configuration Retry
  165
Chapter 9. Dma Controller

166
- M Odes of O Peration
  167
- Figure 9-1 Round -Robin Priority
  168
- Source and Destination
  168
- Table 9-1 Block and Slicet
  169
- Slice Transfers
  169
- Chain Mode
  171
- Bit G-Bus I/O
  172
- Restarting a Disabled Channel
  173
- R Egisters
  174
- Channel Control Registers (CCR0 - CCR7)
  175
- Table 9-3 Channel Controlr
  176
- Table 9-4 Channel Statusr
  178
- Channel Status Register (CSR0 – CSR7)
  178
- Table 9-5 Source Addressr
  179
- Source Address Registers (SAR0 - SAR7)
  179
- Table 9-6 Destination Address
  180
- Table 9-7 Current Byte Count
  180
- Destination Address Register (DAR0 - DAR7)
  180
- Table 9-8 Next Record Pointer
  181
- Table 9-9 Global Control and
  181
- Next Record Pointer Registers (NRPR0 – NRPR7)
  181
- C790 Bus Error Address Register (CBEADDR)
  182
- Table 9-11 G-Bus Error Address
  183
- Table 10-1 Timer Modes Andc
  184
- F Eatures
  184
- Figure 10-1 Timer Modulec
  185
- B Lock D Iagrams
  185
- Figure 10-2 Timer 0, Timer
  186
- S Ignals
  187
- Table 10-3 Timer /Counterc
  188
- C Onfiguration R Egisters
  188
- Table 10-4 Field Descriptions for Table 10-5 Fields Descriptions of
  189
Chapter 10 . Programmable Timer/Counters

189
Chapter 12 . 10/100 Ieee802.3 Media Access Controller

210
- C790 and MAC DMA
  210
- MAC and MII
  211
  - MII (M Edium I Ndependent I Nterface )
    212
  - Mac R Egisters and C Ounters
    213
- Table 12-4 MIIM
  215
- Register Functionality and Field Descriptions
  216
- Counters
  236
- Figure 12-3 Fields of MIIM C
  241
- MIIM (Media Independent Interface Management)
  241
- Figure 12-4 Fields of MIIM D
  242
- Figure 12-5 Imperfect Filtering of
  242
- Address Filtering
  242
- FIFO Addresses
  244
- Figure 12-6 Descriptor Ring and Figure 12-7 Receive Descriptor
  245
- M Emory O Rganization (F Rame D Escriptor )
  245
- Receive Descriptors
  246
- Figure 12-8 Transmit Descriptor
  248
- Transmit Descriptors
  248
- F Unctional D Escription
  250
- FIFO Operation
  253
- MII Interface
  257
- O Verview
  261
Chapter 13 . Removed

262
Chapter 14 . Uarts with Fifos

262
- Key Features
  262
- Receive Operation
  263
- Uart D Evice R Egister D Escription
  264
- Receive Buffer Register (RBR0, RBR1)
  266
- Line Status Registers (LSR0,LSR1)
  268
- FIFO Control Registers (FCR0, FCR1)
  270
- Interrupt Identification Registers (IIR0, IIR1)
  271
- Interrupt Enable Registers (IER0, IER1)
  273
- Modem Status Registers (MSR0, MSR1)
  274
- Scratch Registers (SCR0, SCR1)
  275
- Divisor Latch LS and MS Registers (DLL, DLM)
  276
  - S Pecial F Eatures
    277
  - I Mplemented Restrictions
    278
  - O Verview
    279
  - B Oot M Emory S Equencer for W Ord a Ccess (Bm/W)
    281
Chapter 15 . Serial Port Interface

283
- Boot ROM (64 KB)
  283
  - Tsei O Verview
    285
  - Tsei T Ransfers
    286
- SDMISO and SDMOSI
  287
- Cpha Equals 1 Format
  288
- Mcu I Nterface
  289
- Tsei Registers
  290
  - Tsei Status Register (Sesr)
    291
  - TSEI Data Register (SEDR)
    294
  - Tsei S Ystem E Rrors
    295
  - Toshiba Mode
    296
- Mode
  297
Chapter 16. Clocks

298
- F Eatures
  299
- D Iagram
  301
- O Peration
  302
- P Eripheral M Odule C Lock
  303
- SPI Clock
  304
Chapter 17. Pins

305
- Jtag B Oundary S Can External Test Chain Configuration
  309

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