Toshiba TLCS-900/H1 Series Manual page 349

bit Symbol
EP1_FULL_A
USBINTFR2
(07F1H)
Read/Write
Prohibit to
Reset State
read
Function
-modify
-write
Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.)
bit Symbol EP3_FULL_A
USBINTFR3
(07F2H)
Read/Write
Reset State
Prohibit to
Function
read
-modify
-write
Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.)
•
•
Note: The EPx_FULL_A/B and EPx_Empty_A/B flags are not status flags. Therefore, check DATASET register to
determine if the FIFO-status is needed.
7 6
EP1_Empty_A EP1_FULL_B
R/W R/W R/W
0 0
When read 0: Not generate interrupt
1: Generate interrupt
7 6
EP3_Empty_A EP3_FULL_B
R/W R/W R/W
0 0
When read 0: Not generate interrupt
1: Generate interrupt
When write 0: Clear flag
1: −
EPx_FULL_A/B:
(When transmitting)
This is set to "1" when CPU full write data to FIFO_A/B.
(When receiving)
This is set to "1" when UDC full receive data to FIFO_A/B.
EPx_Empty_A/B:
(When transmitting)
This is set to "1" when FIFO become empty after transmission.
(When receiving)
This is set to "1" when FIFO becomes empty after CPU reads all data from FIFO.
5 4 3
EP1_Empty_B EP2_FULL_A
R/W R/W
0 0 0
When write 0: Clear flag
5 4 3
EP3_Empty_B
R/W
0 0
92CF30-347
TMP92CF30
2 1
EP2_Empty_A EP2_FULL_B EP2_Empty_B
R/W R/W
0 0
1: −
2 1
2009-06-12
0
R/W
0
0