Toshiba TLCS-900/H1 Series Manual page 35

Original cmos 32-bit microcontroller

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Clock doubler (PLL)

PLL0 outputs the f

frequency oscillator can be used as external oscillator, even though the internal clock is

high-frequency.

Since Reset initializes PLL0 to stop status, so setting to PLLCR0 and PLLCR1-register is

needed before use.

As with an oscillator, this circuit requires time to stabilize. This is called the lock-up time

and it is measured by a 12-stage binary counter. Lock-up time is about 0.41ms at f

PLL (PLL1) which is special for USB is built in. Lock-up time is about 0.82ms at f

10MHz measured by 13-stage binary counter.

Note1: Input frequency range for PLL

The input frequency range (High frequency oscillation) for PLL is as follows:

= X to X MHz (Vcc = 1.4 to 1.6V)

Note2: PLLCR0<LUPFG>

The logic of PLLCR0<LUPFG> is different from 900/L1's DFM.

Exercise care in determining theend of lock-up time.

Note3: PLLCR1<PLL0>, PLLCR1<PLL1>

It is not possible to turn ON both PLL0 and PLL1 simultaneously.

If turning ON simultaneously, one PLL should be turn ON after finishing the lock up of the other PLL.

Table 3.4.2 shows the frequency of f

clock signal, which is 12 or 16 times as fast as f

Table 3.4.2 The frequency of f

when using PLL and clock gear at f

Frequency of f

. A low-speed