Toshiba TLCS-900/H1 Series Manual page 366

3.16.3.13 EPx_STATUS Register (x: 0 to 7)
EP0_STATUS bit Symbol
(0790H)
Read/Write
Reset State
EP1_STATUS bit Symbol
(0791H)
Read/Write
Reset State
EP2_STATUS bit Symbol
(0792H)
Read/Write
Reset State
EP3_STATUS bit Symbol
(0793H)
Read/Write
Reset State
EP4_STATUS bit Symbol
(0794H)
Read/Write
Reset State
EP5_STATUS bit Symbol
(0795H)
Read/Write
Reset State
EP6_STATUS bit Symbol
(0796H)
Read/Write
Reset State
EP7_STATUS bit Symbol
(0797H)
Read/Write
Reset State
Note: EP4, 5, 6 and 7_STATUS registers are not used in the TMP92CF30.
TOGGLE Bit (Bit6)
0: TOGGLE
1: TOGGLE
SUSPEND (Bit5)
0: RESUME
1: SUSPEND
These registers are status registers for each endpoint. The <SUSPEND> is common
to all endpoints.
7 6
TOGGLE
R
0
7 6
TOGGLE
R
0
7 6
TOGGLE
R
0
7 6
TOGGLE
R
0
7 6
TOGGLE
R
0
7 6
TOGGLE
R
0
7 6
TOGGLE
R
0
7 6
TOGGLE
R
0
Bit0
Bit1
5 4
SUSPEND STATUS[2] STATUS[1]
R R
0 1
5 4
SUSPEND STATUS[2] STATUS[1]
R R
0 1
5 4
SUSPEND STATUS[2] STATUS[1]
R R
0 1
5 4
SUSPEND STATUS[2] STATUS[1]
R R
0 1
5 4
SUSPEND STATUS[2] STATUS[1]
R R
0 1
5 4
SUSPEND STATUS[2] STATUS[1]
R R
0 1
5 4
SUSPEND STATUS[2] STATUS[1]
R R
0 1
5 4
SUSPEND STATUS[2] STATUS[1]
R R
0 1
This bit shows status of toggle sequence bit.
This bit shows status of UDC power management.
In the SUSPEND status, access to UDC is limited.
For details, refer to 3.16.9.
92CF30-364
3 2 1
STATUS[0] FIFO_DISABLE STAGE_ERR
R R R
1 1 0
3 2 1
STATUS[0] FIFO_DISABLE STAGE_ERR
R R R
1 1 0
3 2 1
STATUS[0] FIFO_DISABLE STAGE_ERR
R R R
1 1 0
3 2 1
STATUS[0] FIFO_DISABLE STAGE_ERR
R R R
1 1 0
3 2 1
STATUS[0] FIFO_DISABLE STAGE_ERR
R R R
1 1 0
3 2 1
STATUS[0] FIFO_DISABLE STAGE_ERR
R R R
1 1 0
3 2 1
STATUS[0] FIFO_DISABLE STAGE_ERR
R R R
1 1 0
3 2 1
STATUS[0] FIFO_DISABLE STAGE_ERR
R R R
1 1 0
TMP92CF30
0
R
0
0
R
0
0
R
0
0
R
0
0
R
0
0
R
0
0
R
0
0
R
0
2009-06-12