Toshiba TLCS-900/H1 Series Manual page 418

Original cmos 32-bit microcontroller

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Table of Contents

Bus Interface and Access to FIFO

(1) CPU bus interface

The UDC prepares two types of FIFO access, single packet and dual packet. In

single packet mode, FIFO capacity that is implemented by hardware is used as large

FIFO. In dual packet mode, FIFO capacity is divided into two and used as two FIFOs.

It is also used as an independent FIFO. Even if the UDC is transmitting and

receiving to USB host, it can be used as an efficient bus by possible load to FIFO.

But control transfer type receives only single packet mode.

Epx_SINGLE signal in dual packet mode must be fixed to "0". If this signal is fixed

to "0", FIFO register runs in single mode.

Sample: Where endpoint 1 is used to dual packet of payload 64 bytes.

EP1_FIFO size

EP1_SINGLE signal

EP1 Descriptor setting

Max payload size

Transfer mode

Prepare 128 bytes