3.18.1
Block Diagram
I2S0CTL
<CLKS0>
f
SYS
f
PLL
<CNTE0>
<CK07:00>
0 1
32bit
64-byte FIFO0
(2 bytes×32)
Counter
8-bit
Stop
Counter
I2S0CTL
6-bit
Counter
I2S0C
I2S0C
<WS05:00>
Clock Generator
31
0 1
31
64-byte FIFO1
(2 bytes×32)
FIFO Control
Write Pointer
Read Pointer
Figure 3.18.1 I
92CF30-473
I2S0CTL
<EDGE0>
I2SCKO
I2SCKO
Invert
Stop
I2S0CTL
<TXE0,CLKE0>
I2SWS
Control
I2S0CTL
<TXE0>
Data Selector
Interrupt
Control
I2S0CTL
<DTFMT01:00
DIR0, BIT0, WLVL0>
Request Signal Output to ADC
(Supported in channel 0 only)
2
S Block Diagram
TMP92CF30
I2S0CKO
I2S0WS
INTI2S0
I2S0DO
2009-06-12