Toshiba TLCS-900/H1 Series Manual page 536

Original cmos 32-bit microcontroller

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3.22.2.8 Storing and Read of AD Conversion Results

higher-order/lower-order registers (ADREG0H/L∼ ADRG5H/L) for the normal AD

conversion (ADREG0H/L to ADREG5H/L are read-only registers)

In the channel-fix repeat conversion mode, AD conversion results are stored into

ADREG0H/L to ADREG3H/L one after another. In other modes, the conversion results

of channels AN0, AN1, AN2, AN3, AN4, and AN5 are each stored into ADREG0H/L,

ADREG1H/L, ADREG2H/L, ADREG3H/L, ADREG4H/L, and ADREG5H/L.

Table 3.22.2 shows the correspondence between analog input channels and AD

conversion result registers.

Table 3.22.2 Correspondence between analog input channels and AD conversion result registers

Analog input channel

Note: In order to detect overruns without omission, read the conversion result storage register's higher-order bits first,

and than read the lower-order bits next. As this result, receiving the result of OVRn = "0" and ADRnRF = "1" for

overruns existing in the lower-order bits means that a correct conversion result has been obtained.

3.22.2.9 Data Polling

To process AD conversion results by using data polling without using interrupts,

perform a polling on ADMOD0<EOS>. After confirming that ADMOD0<EOS> is set to

"1," read the AD conversion storage register.

AD Conversion result registers

Other conversion

modes than shown in

Channel-fix repeat

conversion mode

(per 4 times)