Toshiba TLCS-900/H1 Series Manual page 462

(k) RXE
In the UNIT–mode reception, writing a "1" to this bit enables the reception of only
one UNIT-size data.
When reading the receive data register (SPIRD) while this bit is kept enabled, one
more UNIT data is additionally received.
In Sequential mode, writing a "1" to this bit enables the sequential data reception
until the 32-byte FIFO buffer becomes full. The state of this bit can be changed even
during the data reception. If this bit is cleared to "0" during a data reception, the
reception is stopped after completing the reception of the UNIT data currently being
received.
[Data Transmission/Reception Modes]
This SPI Controller supports six operating modes as listed below.
These are specified by the FDPXE, RXMOD, RXE, TXMOD, TXE bits.
Operating Mode
(1) UNIT transmission
(2) Sequential transmission
(3) UNIT reception
(4) Sequential reception
(5) UNIT transmission and
reception
(6)Sequential transmission
and reception
x: Don't care
Table 3.17.2 Data Transmission Reception Modes
Bit Settings
<FDPXE> <TXMOD> <TXE>
0 0
0 1
0 x
0 x
1 0
1 1
92CF30-460
<RXMOD> <RXE>
1 x x
1 x x
x 0 1
x 1 1
1 0 1
1 1 1
TMP92CF30
Description
Transmit the SPITD data per UNIT
Transmit the FIFO data sequentially
Receive only one UNIT-size data
Automatically receive data if FIFO buffer
has any empty space
Transmit/receive one UNIT-size data with
the addresses of transmit/receive data
aligned on UNIT-size boundaries
Transmit/receive data sequentially with the
addresses of transmit/receive data aligned
on UNIT-size boundaries
2009-06-12