Toshiba TLCS-900/H1 Series Manual page 381

3.16.3.25 EPx_SINGLE Register
EPx_SINGLE1 bit Symbol
(07D1H)
Read/Write
Reset State
Note: Endpoint 3 support only SINGLE mode in the TMP92CF30.
Bit number
0: No use
1: EP1_SINGLE
2: EP2_SINGLE
3: EP3_SINGLE
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
When EPx_SELECT bit is "1", EPx_SINGLE bit becomes valid in the following content.
If setting content of EPx_SINGLE bit to valid, set EPx_SELECT bit to "1".
3.16.3.26 EPx_BCS Register
EPx_BCS1 bit Symbol
(07D3H)
Read/Write
Reset State
Bit number
0: No use
1: EP1_BCS
2: EP2_BCS
3: EP3_BCS
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
Always write "1" to EPx_BCS bit regardless of whether endpoint is used or not.
If setting content of EPx_BCS bit to valid, set EPx_SELECT bit to "1".
This register sets mode of FIFO in each endpoint (SINGLE/DUAL).
7 6
EP3_SELECT EP2_SELECT EP1_SELECT
R/W R/W
0 0
0: DUAL mode
0: Invalid
This register sets mode of access to FIFO in each endpoint.
7 6
EP3_SELECT EP2_SELECT EP1_SELECT
R/W R/W
0 0
0: Reserved
0: Invalid
5 4
EP3_SINGLE EP2_SINGLE EP1_SINGLE
R/W
0
1: SINGLE mode
1: Valid
5 4
EP3_BCS
R/W
0
1: CPU access
1: Valid
92CF30-379
3 2 1
R/W R/W R/W
0 0
3 2
EP2_BCS EP1_BCS
R/W R/W
0 0
TMP92CF30
0
0
1 0
R/W
0
2009-06-12