Toshiba TLCS-900/H1 Series Manual page 645

(20) I S
2
Symbol Name
Address
2
I S
Transmi-
1800H
ssion
I2S0BUF
(Prohibit
RMW)
Buffer
Register0
1808H
2
I S
Control
I2S0CTL
Register0
1809H
180AH
2
I S0
Divider
I2S0C Value
Setting
Register
180BH
15 14 13 12 11
B015 B014 B013 B012 B011
31 30 29 28 27
B031 B030 B09 B028 B027
TXE0 *CNTE0
R/W
0 0
Transmit Counter
0: Stop control
1: Start 0: Clear
1: Start
CLKS0
R/W
0
Source
clock
0: f
SYS
1: f
PLL
CK07 CK06 CK05
0 0
WS05
92CF30-643
10 9 8 7 6
B010 B009 B008 B007 B006
W
Undefined
Transmission buffer register (FIFO)
26 25 24 23 22
B026 B025 B024 B023 B022
W
Undefined
Transmission buffer register (FIFO)
DIR0 BIT0
0 0
Transmi- Bit length
ssion start
BIT 0: 8 bits
0:MSB
1:16 bits
1:LSB
FSEL0 TEMP0
R/W R
0 1
Stereo
Condition of
transmission
/monaural
FIFO
0: Stereo
0: data
1: Monaural
1: None
data
CK04 CK03
R/W
0 0 0
Divider value for CK signal (8-bit counter)
WS04 WS03
0 0 0
Divider value for WS signal (6-bit counter)
TMP92CF30
5 4 3 2
B005 B004 B003 B002 B001
21 20 19 18 17 16
B021 B020 B019 B018 B017
DTFMT01 DTFMT00 SYSCKE0
R/W
0 0
Output format System
clock
2
00: I S 10: Right
0:Disable
01: Left 11:Reserved
1:Enable
WLVL0 EDGE0
R/W
0 0
WS level Clock Clock
edge for enable
data
(After trans-
0:low left
output
mission)
1:high left
0: Falling
0:Operate
1: Rising
1:Stop
CK02 CK01
0 0
WS02 WS01
R/W
0 0
2009-06-12
1 0
B000
B016
0
CLKE0
0
CK00
0
WS00
0