Toshiba TLCS-900/H1 Series Manual page 368

Original cmos 32-bit microcontroller

Hide thumbs Also See for TLCS-900/H1 Series:

Table of Contents

FIFO_DISABLE (Bit1)

0: FIFO enabled

1: FIFO disabled

STAGE_ERROR (Bit0)

This bit symbol shows FIFO status except for EP0.

If the FIFO is set to disabled, the UDC transmits NAK

handshake for all transfers. Disabled or enabled status is set the

COMMAND register. This bit is cleared to "0" when transfer type

This bit symbol shows that the status stage has not been

terminated correctly. ERROR is set when a status stage is not

terminated correctly and a new SETUP token is received.

When this bit is "1", this bit is cleared to "0" by read

EP0_STATUS register. This bit is not cleared even if normal

control transfer or other transfer is executed after. To clear, read

this bit. When software transaction is finished and UDC writes

EOP register, UDC shifts to status register and

termination of status stage. In this case, if software is needed to

confirm that the status stage has been terminated correctly, when

a new request flag is received, it is possible to confirm whether or

not the last request has been terminated correctly. It can also be

confirmed, when a new request flag is asserted, whether or not

the last request has been cancelled before completion.