Toshiba TLCS-900/H1 Series Manual page 465

Original cmos 32-bit microcontroller
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Differences Between the UNIT-mode and Sequential-mode Receptions
The UNIT-mode reception receives only one UNIT-size data. The UNIT mode for the
data reception can be selected by writing a "0" to the SPICT<RXMOD> bit.
The receive FIFO is disabled in UNIT mode. Writing a "1" to the SPICT<RXE> bit
initiates a receive operation of one UNIT data. Then, the transmission is terminated after
storing the received data into the receive data register (SPIRD). To perform one-UNIT data
reception, read the SPIRD register after writing a "0" to the SPICT<RXE> bit. If the SPIRD
register is read again when the SPICT<RXE> bit is set to "1", one-UNIT data is
additionally received. During the data reception, it is prohibited to change the reception
mode from Sequential to UNIT, or vice versa.
In this mode, the RFUL and REND interrupts are generated when the receive data is
loaded into the SPIRD register from the receive shift register.
The Sequential-mode reception automatically receives the data as long as the receive
FIFO has any empty space. The Sequential mode is selected by writing a "1" to the
SPICT<RXMOD> bit. The 32-byte receive FIFO is disabled in this mode. In this reception
mode, the data reads from the receive FIFO must be performed in 16-byteunits. Otherwise,
the RFUL interrupt is not properly generated.
Received data is stored into the receive FIFO by writing a "1" to the SPICT<RXE> bit.
This mode of reception keeps receiving the next data automatically unless the data
receive FIFO becomes full (32 bytes). Therefore, the reception continues sequentially
without stopping at every UNIT-sized reception. During the data reception, it is prohibited
to change the reception mode from Sequential to UNIT, or vice versa.
Writing a "0" to the SPICT<RXE> bit during a reception stops the data reception after
completing the reception of the UNIT data currently being received.
The RFUL interrupt is generated when the size of data stored into the FIFO reaches 16
or 32 bytes. The REND interrupt is generated when the 32-byte receive FIFO becomes full.
92CF30-463
TMP92CF30
2009-06-12

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