Toshiba TLCS-900/H1 Series Manual page 468

Original cmos 32-bit microcontroller

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(3-1) SPI Status Register (SPIST)

The SPIST register contains three bits that indicates the status of data communication.

For UNIT-mode transmission, this bit is cleared to "0" when the transmit register

(SPITD) contains valid data; otherwise, it is set to "1".

For Sequential-mode transmission, this bit is set to "1" when the transmit FIFO

buffer contains no valid data.

This bit is cleared to "0" when the SPITD register or the transmit FIFO contains

valid transmit data, and also when the transmission is in progress. This bit is set to "1"

after completing the data transmission where the SPITD register and the transmit

FIFO contain no valid data.

For UNIT-mode reception, this bit is set to "1" when completing the data reception

and valid data is stored into the receive data register (if there is any valid data). This

bit is cleared to "0" when the receive register (SPIRD) contains no valid data, or when

the reception is in progress.

For Sequential-mode reception, this bit is set to "1" when the 32-byte receive FIFO is

full with the valid data after completing the reception of the last data. This bit is

cleared to "0" when there is still an empty space of one byte or more in the FIFO.

The RFUL flag does not exist because its function is exactly the same as the REND

SPIST Register

Figure 3.17.9 SPIST Register

Transmission

0: Reception

Transmission

or not having

receive data

transmit data

1: Reception

Transmission