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Toshiba TXZ Series Reference Manual

Toshiba TXZ Series Reference Manual

32-bit risc microcontroller, serial peripheral inteface tspi-b
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TXZ Family
Serial Peripheral Interface
32-bit RISC Microcontroller
TXZ Family
Reference Manual
Serial Peripheral Inteface
(TSPI-B)
Revision 3.0
2019-02
1 / 67
2019-02-28
Rev. 3.0
© 2017-2019
Toshiba Electronic Devices & Storage Corporation

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Summary of Contents for Toshiba TXZ Series

  • Page 1 TXZ Family Serial Peripheral Interface 32-bit RISC Microcontroller TXZ Family Reference Manual Serial Peripheral Inteface (TSPI-B) Revision 3.0 2019-02 1 / 67 2019-02-28 Rev. 3.0 © 2017-2019 Toshiba Electronic Devices & Storage Corporation...

  • Page 2: Table Of Contents

    TXZ Family Serial Peripheral Interface Table of Contents Preface ................................. 5 Related document ..............................5 Conventions ................................6 Terms and Abbreviation ............................8 Outline ................................9 Configuration ............................... 14 Operation description ..........................16 3.1. Basic operation ..............................16 3.1.1. Clock supply ................................16 3.1.2.
  • Page 3 TXZ Family Serial Peripheral Interface 3.3.10. DMA request................................47 3.3.10.1. Transmit DMA request ..............................47 3.3.10.2. Receive DMA request ..............................47 3.3.11. Coordinated movements by the completion of communication ................47 3.3.12. Software reset ................................47 Registers ..............................48 4.1. Register List ..............................48 4.2.
  • Page 4 TXZ Family Serial Peripheral Interface List of Figures Figure 2.1 Block diagram of TSPI ......................14 Figure 3.1 Data format ..........................17 Figure 3.2 MSB first (32-bit data without a parity bit)................18 Figure 3.3 MSB first (16-bit data without a parity bit)................19 Figure 3.4 LSB first (32-bit data without a parity bit)................

  • Page 5: Preface

    TXZ Family Serial Peripheral Interface Preface Related document Document name Clock Control and Operation Mode Exception Input/Output Ports Product Information 2019-02-28 5 / 67 Rev. 3.0...

  • Page 6: Conventions

    TXZ Family Serial Peripheral Interface Conventions ● Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 – It is possible to omit the “0b” when the number of bit can be distinctly understood from a sentence.
  • Page 7 TXZ Family Serial Peripheral Interface *********************************************************************************************************************** Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. *********************************************************************************************************************** The flash memory uses the Super Flash® technology under license from Silicon Storage Technology, Inc. Super Flash®...

  • Page 8: Terms And Abbreviation

    Serial Peripheral Interface Terms and Abbreviation Some of abbreviations used in this document are as follows: Acknowledgement Direct Memory Access FIFO First-In First-Out Least Significant Bit Most Significant Bit Serial Input/Output TSPI Toshiba Serial Peripheral Interface 2019-02-28 8 / 67 Rev. 3.0...

  • Page 9: Outline

    TXZ Family Serial Peripheral Interface Outline TSPI(Serial Peripheral Interface) has four operation mode as SPI/SIO mode, and the clock master/ clock slave mode. One channel/unit which is built-in TSPIxTXD,TSPIxRXD,TSPIxSCK,TSPIxCS0,TSPIxCS1, TSPIxCS2,TSPIxCS3, and TSPIxCSIN can be transmit and receive circuit. functions are as below. 2019-02-28 9 / 67 Rev.

  • Page 10: Table 1.1 Functional Outline (Spi Mode, Master)

    TXZ Family Serial Peripheral Interface Table 1.1 Functional outline (SPI mode, master) Function classification Function A Functional Description or the range The clock inputted from the prescaler can be Transmission Prescaler dividing selection divided 1/1,1/2,1/4..up to 1/512. Speed The input clock to baud rate generator. Control Baud rate generator dividing 1/N x 1/2 (N= 1 to 16)

  • Page 11: Table 1.2 Functional Outline (Spi Mode, Slave)

    TXZ Family Serial Peripheral Interface Table 1.2 Functional outline (SPI mode, slave) Function classification Function A Functional Description or the range The data length can be setup in a 1-bit unit. Data length 8 to 32bits (with no parity) 7 to 31bits (with parity) Data Selection of with parity/without parity is possible.

  • Page 12: Table 1.3 Functional Outline (Sio Mode, Master)

    TXZ Family Serial Peripheral Interface Table 1.3 Functional outline (SIO mode, master) Function classification Function A Functional Description or the range The clock inputted from the prescaler can be Prescaler dividing selection Transmission divided 1/1,1/2,1/4..up to 1/512. speed The input clock to baud rate generator. Control Baud rate generator dividing 1/N x 1/2 (N= 1 to 16)

  • Page 13: Table 1.4 Functional Outline (Sio Mode, Slave)

    TXZ Family Serial Peripheral Interface Table 1.4 Functional outline (SIO mode, slave) Function classification Function A Functional Description or the range The data length can be setup in a 1-bit unit. Data length 8 to 32bits (with no parity) 7 to 31bits (with parity) Data Selection of with parity/without parity is possible.

  • Page 14: Configuration

    TXZ Family Serial Peripheral Interface Configuration The block diagram of the TSPI and the signal list are shown. TSPI Baud Rate <SWRST> TSPI Control Register Register 0 Operation clock [TSPIxBR] [TSPIxCR0] Clock for pre-scalar Baud Rate ΦTx Pre-scalar ΦT0 Generator Trigger input for start transition TSPIxTRG...

  • Page 15: Table 2.1 List Of Signals

    TXZ Family Serial Peripheral Interface Table 2.1 List of Signals Signal symbol Signal name Reference manual Clock Control and Operation Mode (Note) Operation clock Input Product Information 2 ΦT0 Clock for prescaler Clock Control and Operation Mode Input 3 TSPIxSCK Serial clock output/ Serial clock input Input/Output Ports Input/Output...

  • Page 16: Operation Description

    TXZ Family Serial Peripheral Interface Operation description 3.1. Basic operation 3.1.1. Clock supply When TSPI is used, the corresponding clock enable bits should be set to “1” (Clock supply) in fsys supply stop register A ([CGFSYSENA] and [CGFSYSMENA]), fsys supply stop register B ([CGFSYSENB] and [CGFSYSMENB]), and fc supply stop register ([CGFCEN]).

  • Page 17: Data Format

    TXZ Family Serial Peripheral Interface 3.2. Data Format When specifying the transfer direction MSB/LSB first and frame length, set up [TSPIxFMTR0](TSPI format control register 0). When specifying the enable parity and even/odd parity, set up [TSPIxFMTR1](TSPI format control register 1). Note: When the parity function is enabled, data length is 31 bits at maximum.

  • Page 18: Data Format Without Parity

    TXZ Family Serial Peripheral Interface 3.2.1. Data Format without Parity If data format is without parity bit, the length of frame must be the same as the length of data. For example, when the length of data is 10-bit, set "001010" to [TSPIxFMTR0]<FL[5:0]>. The data in the transmit FIFO is transferred remaining unchanged to the shift register.

  • Page 19: Figure 3.3 Msb First (16-Bit Data Without A Parity Bit)

    TXZ Family Serial Peripheral Interface (2) MSB First Transfer (16-bit data without a parity bit, 16-bit data frame length) Figure 3.3 shows a transmit/receive operation (without parity, MSB first, 32-bit data length). In the transmission, data in the transmit FIFO is copied to D15 through D0 in the shift register. Transmit data copied to shift register is transferred sequentially from D15 through D0 on serial clock.

  • Page 20: Figure 3.4 Lsb First (32-Bit Data Without A Parity Bit)

    TXZ Family Serial Peripheral Interface (3) LSB First Transfer (32-bit data without a parity bit, 32-bit frame length) Figure 3.4 shows a 32-bit data length transmit/receive operation when parity function is disabled. In the transmission, data in the transmit FIFO is sorted bit by bit when the data is copied to the shift register. Transmit data copied to the shift register is transferred from D0 until reaching 32-bit shifted data on serial clock.

  • Page 21: Figure 3.5 Lsb First (16-Bit Data Without A Parity Bit)

    TXZ Family Serial Peripheral Interface (4) LSB First Transfer (16-bit data without a parity bit, 16-bit frame length) Figure 3.5 shows a 16-data length transmit/receive operation (without a parity bit, MSB first, 32-bit data length). In the transmission, data in the transmit FIFO is sorted bit by bit when the data is copied to the shift register. Transmit data copied to shift register is transferred from D15 until reaching 16-bit shifted data on serial clock.

  • Page 22: Data Format With A Parity

    TXZ Family Serial Peripheral Interface 3.2.2. Data Format with a Parity If data format is with parity bit, frame length is specified as a data length including a parity bit. For example, when data length is 10-bit, set "001011" to [TSPIxFMTR0]<FL[5:0]>. If data format is with parity bit, a parity bit is automatically added to data in the transmit FIFO and the data is copied to shift register.

  • Page 23: Figure 3.7 Msb First (15-Bit Data With Parity)

    TXZ Family Serial Peripheral Interface (2) MSB first transfer (15-bit data with parity, frame length is 16-bit) Figure 3.7 shows a 15-bit data length transmit/receive operation (with a parity bit, MSB first, 15-bit data length). A frame length is 16-bit data length including a parity bit. In the transmission, data D14 through D0 in the transmit FIFO is copied to D15 through D1 in the shift register.

  • Page 24: Figure 3.8 Lsb First (31-Bit Data With Parity)

    TXZ Family Serial Peripheral Interface (3) LSB first transfer (31-bit data with parity; frame length is 32-bit) Figure 3.8 shows a 31-bit data length transmit/receive operation (with a parity bit, LSB first, 31-bit data length). In the transmission, data D30 through D0 in the transmit FIFO is sorted bit by bit and the data is copied to bit 31 through bit 1 in the shift register.

  • Page 25: Figure 3.9 Lsb First (15-Bit Data With Parity)

    TXZ Family Serial Peripheral Interface (4) LSB first transfer (15-bit data with a parity bit, 16-bit frame length) Figure 3.9 shows a 15-bit data length transmit/receive operation (with a parity bit, LSB first, 15-bit data length). A frame length is 16-bit data length including a parity bit. In the transmission, data D14 through D0 in the transmit FIFO are sorted bit by bit and the data is copied to D17 from D31 in the shift register.

  • Page 26: Operation

    TXZ Family Serial Peripheral Interface 3.3. Operation 3.3.1. Transfer clock 3.3.1.1. Master operation The transfer clock generation circuit is shown Figure 3.10. Prescaler Prescaler Clock 1/16 1/32 1/64 1/128 1/256 1/512 ΦT0 ΦTx Baud Rate Transfer clock Genenrator (TSPIxSCK) Figure 3.10 Transfer clock generation circuit The prescaler dividing ΦT0 from 1/1 to 1/512 (ΦT0 to ΦT256).

  • Page 27: Slave Operation

    TXZ Family Serial Peripheral Interface Table 3.1 Example of f /ΦT0/ΦTx/ transfer clock and usability Condition: [TSPIxCR2]<RXDLY>=1, f /transfer clock≥4, transfer clock=ΦTx/2 product transfer clock≤20MHz transfer clock ΦT0(MHz) ΦTx(MHz) (MHz) Usability TSPIxSCK(MHz)        12.5 ...

  • Page 28: Communication Mode

    TXZ Family Serial Peripheral Interface 3.3.2. Communication mode The TSPI has two communication modes: SIO mode and SPI mode. Communication mode is specified by [TSPIxCR1]<TSPIMS>. 3.3.2.1. SPI mode When write "0" to [TSPIxCR1]<TSPIMS>(Communication mode selection), the TSPI operates in SPI mode. In SPI mode, one master device can be connected with four slave devices via TSPIxSCK(clock input/output), TSPIxCS0/1/2/3(Chip select output), TSPIxCSIN(Chip select input), TSPIxTXD(data transmission), and TSPIxRXD(data reception).

  • Page 29: Sio Mode

    TXZ Family Serial Peripheral Interface 3.3.2.2. SIO mode When write "1" to [TSPIxCR1]<TSPIMS>(Communication mode selection), the TSPI operates in SIO mode. In SIO mode, one master device can be connected with one slave device via TSPIxSCK(clock input/output), TSPIxTXD(data transmission), TSPIxRXD(data reception). ●...

  • Page 30: Data Length And Fifo Operation

    TXZ Family Serial Peripheral Interface 3.3.3.1. Data Length and FIFO Operation Data register is 32-bit width. The FIFO of the TSPI adjusts data to 32-bit width for most efficient DMA transfer. The following description is an example of receive FIFO operation. Transmission is the same operation except data direction.

  • Page 31: Figure 3.12 Operation In 17 To 32-Bit Data Length

    TXZ Family Serial Peripheral Interface (2) Data length 17 to 32-bit If 17 to 32-bit data length are used, two stages of the FIFO are used for one frame. The FIFO has 8 stages, so that it can store four frame data up to four stage levels. Figure 3.12 Operation in 17 to 32-bit data length Input data to TSPIxRXD is captured in the shift register.

  • Page 32: Communication Operation Mode

    TXZ Family Serial Peripheral Interface 3.3.4. Communication Operation mode 3.3.4.1. Full duplex communication mode Figure 3.13 shows an operation example of full duplex communication in continuously transfer (32-bit frame length, no parity, one-stage of FIFO). ([TSPIxCR2]<TIDLE[1:0]>=10) [TSPIxCR]<TRXE> [TSPIxDR] [TSPIxSR]<TLVL[3:0]> [TSPIxSR]<RLVL[3:0]> Figure 3.13 Operation example of full duplex communication Write "1"...
  • Page 33 TXZ Family Serial Peripheral Interface Since one stage of the receive FIFO is buffered, [TSPIxSR]<RLVL> becomes "1". Since [TSPIxSR]<RLVL> changes to "1" from "0", a receive FIFO interrupt (or receive DMA request) occurs. Until the minimum idle time (t ) specified by [TSPIxFMTR0]<CSINT> has elapsed after TSPIxCS0 is deasserted, serial transfer does not start and TSPIxCS0 remains deasserted.

  • Page 34: Transmit Mode

    TXZ Family Serial Peripheral Interface 3.3.4.2. Transmit mode Figure 3.14 shows an operation example of continuously transfer (32-bit frame length, no parity, one-stage of FIFO) in the transmit mode. ([TSPIxCR2]<TIDLE[1:0]>=10) [TSPIxCR]<TRXE> [TSPIxDR] [TSPIxSR]<TLVL[3:0]> [TSPIxSR]<RLVL[3:0]> Figure 3.14 Operation example of transmit mode Write "1"...

  • Page 35: Receive Mode

    TXZ Family Serial Peripheral Interface 3.3.4.3. Receive mode Figure 3.15 shows an operation example of continuously transfer (32-bit length, no parity, one stage of FIFO) in receive mode. ([TSPIxCR2]<TIDLE[1:0]>=10) [TSPIxCR]<TRXE> [TSPIxDR] [TSPIxSR]<TLVL[3:0]> [TSPIxSR]<RLVL[3:0]> Operation example in receive mode Figure 3.15 Write "1"...

  • Page 36: Transfer Mode

    TXZ Family Serial Peripheral Interface 3.3.5. Transfer mode A transfer mode consists of three modes: single transfer, burst transfer and continuously transfer. Single transfer can transfer one frame of data; burst transfer can transfer multiple frames of data; continuously transfer can transfer without specifying the number of transfer frames.

  • Page 37: Data Sampling Timing

    TXZ Family Serial Peripheral Interface 3.3.6. Data sampling timing The data sampling timing can be set by [TSPIxFMTR0]<CKPHA> (Edge selection register for the serial clock). When [TSPIxFMTR0]<CKPHA> = 1is set, data is sampled by the second edge. And when, [TSPIxFMTR0]<CKPHA>=0, by the first edge. Table 3.3 is shown Usability of communication mode and data sampling timing.

  • Page 38: Figure 3.16 Data Sampling Timing Of Spi Mode (Master)

    TXZ Family Serial Peripheral Interface [SPI mode(master)　2nd edge data sampling<CKPHA>=1] <CSnPOL>=0 TSPIxCSn <CSnPOL>=1 <CKPOL>=0 TSPIxSCK <CKPOL>=1 TSPIxTXD Output timing TSPIxRXD Input sampling [SPI mode(master)　1st edge data sampling<CKPHA>=0] Internal <CKPOL>=0 Clock TSPIxSCK Internal <CKPOL>=1 Clock TSPIxTXD Output timing TSPIxRXD Input sampling [SPI mode(master)　1st edge data sampling<CKPHA>=0 Idle period output is Hi-Z<TIDLE>=00] <CSnPOL>=0 TSPIxCSn...

  • Page 39: Figure 3.17 Data Sampling Timing Of Spi Mode (Slave)

    TXZ Family Serial Peripheral Interface [SPI mode(slave)　2nd edge data sampling<CKPHA>=1] <CS0POL>=0 TSPIxCSIN <CS0POL>=1 <CKPOL>=0 TSPIxSCK <CKPOL>=1 TSPIxTXD Output timing TSPIxRXD Input sampling Figure 3.17 Data sampling timing of SPI mode (slave) [SIO mode(master)2nd edge data sampling<CKPHA>=1] <CKPOL>=0 TSPIxSCK <CKPOL>=1 TSPIxTXD Output timing TSPIxRXD Input sampling...

  • Page 40: Special Control

    TXZ Family Serial Peripheral Interface 3.3.7. Special control 3.3.7.1. Polarity of TSPIxCS0/1/2/3 signal and generation timing The polarity of TSPIxCS0/1/2/3 can be individually selected by [TSPIxFMTR0]<CSnPOL>(polarity register of TSPIxCS0/1/2/3/). In the case of [TSPIxFMTR0]<CSnPOL>=0, it becomes negative logic and [TSPIxFMTR0]<CSnPOL>=1, it becomes positive logic. Moreover, the generating timing of TSPIxCS0/1/2/3 can be set up as follows.

  • Page 41: Polarity Of The Clock

    TXZ Family Serial Peripheral Interface 3.3.7.2. Polarity of the Clock To select a polarity of the clock, set [TSPIxFMTR0]<CKPOL>. When [TSPIxFMTR0]<CKPOL>=0, TSPIxSCK outputs "Low" level signal during idle period and the first clock edge is a rising edge. When [TSPIxFMTR0]<CKPOL>=1, TSPIxSCK outputs "High" level signal during idle period and the first clock edge is a falling edge.

  • Page 42: Figure 3.21 Idle State In Spi Mode And The Transmit Pin Status

    TXZ Family Serial Peripheral Interface [TSPIxCR2]<TIDLE[1:0]>=10,[TSPIxFMTR0]<CKHPA>=1: Example of outputting low at idle edge) Idle state in SPI mode and the transmit pin status Figure 3.21 [TSPIxCR2]<TIDLE[1:0]>=10, [TSPIxFMTR0]<CKHPA>=1: Example of outputting low at idle (Undefined) edge) Idle state in SIO mode and the transmit pin status Figure 3.22 2019-02-28 42 / 67...

  • Page 43: Communication Control By Trigger

    TXZ Family Serial Peripheral Interface 3.3.8. Communication control by trigger In the master operation, when [TXPIxCR1]<TRGEN> is set to “1”, the function of the starting communication by generating of a trigger can be used. If "1" is set as [TSPIxCR1]<TRGEN>, when communication is not performed, it will be waiting for a trigger. If a trigger is inputted, it will be automatically set to [TSPIxCR1]<TRXE>=1, and communication will be started.

  • Page 44: Interrupt Request

    TXZ Family Serial Peripheral Interface 3.3.9. Interrupt Request The TSPI has three types of interrupts: receive interrupt, transmit interrupt and error interrupt. Each interrupt is an output consisting of some signals related to interrupts. They are enabled/disabled respectively. Table 3.6 Interrupt events and requests Interrupt request Interrupt event Enable register...

  • Page 45: Transmit Completion Interrupt/Receive Completion Interrupt

    TXZ Family Serial Peripheral Interface 3.3.9.1. Transmit Completion Interrupt/Receive Completion Interrupt (1) Master operation Each single transfer, burst transfer and continuously transfer, transmit completion interrupt occurs (Note) when TSPIxCS0/1/2/3 is deasserted in transmission or full duplex communications. Each single transfer, burst transfer and continuously transfer, receive completion interrupt occurs (Note) when TSPIxCS0/1/2/3 is deasserted in reception or full duplex communications.

  • Page 46: Figure 3.24 Overrun Error And Underrun Error

    TXZ Family Serial Peripheral Interface An underrun and overrun errors occur in slave mode. An underrun error occurs when data does not exist in the transmit FIFO after data in the shift register is transferred completely if the next transfer clock is input. An overrun error occurs when the receive FIFO is full and receive shift register contains data if the next transfer clock is input.

  • Page 47: Dma Request

    TXZ Family Serial Peripheral Interface 3.3.10. DMA request The DMA request has the transmit and receive request. These request have the single and burst request. Supported DMA requests depend on the product. Please refer to reference manual of “Product Information” for details.

  • Page 48: Registers

    TXZ Family Serial Peripheral Interface Registers 4.1. Register List The following table lists the control registers and addresses. Base address Function Peripheral Channel/Unit name TYPE1 TYPE2 TYPE3 0x40098000 0x400CA000 0x4006A000 0x40099000 0x400CA400 0x4006A400 0x4009A000 0x400CA800 0x4006A800 0x4009B000 0x400CAC00 0x4006AC00 0x4009C000 0x400CB000 0x4006B000 0x4009D000...

  • Page 49: Detail Of Register

    TXZ Family Serial Peripheral Interface 4.2. Detail of Register 4.2.1. [TSPIxCR0] (TSPI Control Register 0) Bit Symbol After reset Type Function 31:8 Read as "0". TSPI software reset (Note) Software reset occurs by writing "10" and then "01". SWRST[1:0] By software reset, the transfer operation under execution is forcibly terminated and the value of the control register other than the transfer setting is initialized.

  • Page 50: Tspixcr1] (Tspi Control Register 1)

    TXZ Family Serial Peripheral Interface 4.2.2. [TSPIxCR1] (TSPI Control Register 1) Bit Symbol After reset Type Function 31:16 Read as "0". Trigger control (valid only in Master operation) TRGEN 0: Not used 1: A trigger is valid Communication control (Note1)(Note2)(Note3)(Note4) 0: Communication stops 1: Communication is enabled Full duplex mode/transmission mode...
  • Page 51 TXZ Family Serial Peripheral Interface not started by <TRXE> after the setup to "1" (Communication is enable), when slave operation, state flag [TSPIxSR]<TSPISIUE> is not set to "0" (Modification is enabled). In spite of enable communication in slave device when communication of a master device is not started, please perform re-set it up , after the slave device performs software reset by [TSPIxCR0]<SWRST>.

  • Page 52: Tspixcr2] (Tspi Control Register 2)

    TXZ Family Serial Peripheral Interface 4.2.3. [TSPIxCR2] (TSPI Control Register 2) Bit Symbol After reset Type Function 31:24 Read as "0". Fixed output value function control when TSPIxTXD idles. 00: Hi-z 23:22 TIDLE[1:0] 01: Last data in previous transfer 10: Fixed to low 11: Fixed to high Fixed output value function control when TSPIxTXD underruns.
  • Page 53 TXZ Family Serial Peripheral Interface Transmit DMA control 0: Disabled 1: Enabled When <DMATE> is enabled The DMA request is output when DMATE the transmit FIFO is less than the level set in <TIL>. It does not depend on the state of [TSPIxCR1] <TRXE>. If <DMATE>...

  • Page 54: Tspixcr3] (Tspi Control Register 3)

    TXZ Family Serial Peripheral Interface 4.2.4. [TSPIxCR3] (TSPI Control Register 3) Bit Symbol After reset Type Function 31:2 Read as "0". Clears transmit buffer 0: Invalid 1: Clear TFEMPCLR By writing "1" to <TFEMPCLR>, the internal pointer of the transmit FIFO and pointer of transmit shift register are initialized.

  • Page 55: Tspixfmtr0] (Tspi Format Control Register 0)

    TXZ Family Serial Peripheral Interface 4.2.6. [TSPIxFMTR0] (TSPI Format Control Register 0) Bit Symbol After reset Type Function Transfer direction 0: LSB first 1: MSB first Read as "0". Sets a frame length.(Note1) Sets a data length of one frame including a parity bit. 001000: 8 bits 001001: 9 bits 29:24...
  • Page 56 TXZ Family Serial Peripheral Interface Idle time (Note3) TSPIxCS0/1/2/3 invalidTSPIxCS0/1/2/3 valid time 0000: Prohibited 0001: 1 x TSPIxSCK cycle 0010: 2 x TSPIxSCK cycles 13:10 CSINT[3:0] 0001 0111: 14 x TSPIxSCK cycles 1111: 15 x TSPIxSCK cycles CS deassertion period until the start of next frame of continuously transfer.

  • Page 57: Tspixfmtr1] (Tspi Format Control Register 1)

    TXZ Family Serial Peripheral Interface 4.2.7. [TSPIxFMTR1] (TSPI Format Control Register 1) Bit Symbol After reset Type Function 31:7 Read as "0". Sets a last bit holding time of TSPIxTXD pin in SIO slave mode.(Note1) 000: 2/f 001: 4/f 010: 8/f EHOLD[2:0] 011: 16/f 100: 32/f...

  • Page 58: Tspixsr] (Tspi Status Register)

    TXZ Family Serial Peripheral Interface 4.2.9. [TSPIxSR] (TSPI Status Register) After Bit Symbol Type Function reset TSPI modify status flag 0: Modification is enabled. 1: Modification is disabled. If <TSPISUE> is "0", the TSPI is not transmitting or receiving, thus the register setting can be modified.
  • Page 59 TXZ Family Serial Peripheral Interface 0: Don’t care 1: Flag is cleared. This bit is cleared by writing "1". Transmit FIFO empty flag 0: Data exists in the FIFO. 1: Empty TFEMP When the transmit FIFO is empty, "1" is set. If transmit data is written to the transmit FIFO, this bit is automatically cleared to "0".

  • Page 60: Table 4.2 The Timing Of Write "0" To , And State Of

    TXZ Family Serial Peripheral Interface Table 4.2 The timing of write "0" to <TRXE>, and state of <TSPISUE> Timing of State of <TSPISUE> write “0” to [TSPIxCR1]<TRXE> Master operation Slave operation “1” Before start Clear to “0” (Please performs software reset by transferring [TSPIxCR0]<SWRST>) During transferring...

  • Page 61: Tspixerr] (Tspi Error Flag Register)

    TXZ Family Serial Peripheral Interface 4.2.10. [TSPIxERR] (TSPI Error Flag Register) After Bit Symbol Type Function reset 31:4 Read as "0". Trigger communication error flag 0: No error 1: Error exists When a trigger is input, this bit is set if communication has not been started.

  • Page 62: Example For Use

    TXZ Family Serial Peripheral Interface Example for use For example, the details of starting / stopping operation for every communicate mode and transfer mode are shown in Table 5.1. Table 5.1 Transfer starting and stopping operation in each mode setting (Master) communication Transfer mode Communication start timing...
  • Page 63 TXZ Family Serial Peripheral Interface A reception starts if receive buffer (receive FIFO or receive shift register) is not full. If the receive buffer is full, next frame cannot be transferred. When reading the receive FIFO data, if Burst transfer data in the shift register is automatically transferred to In reception, if <TRXE>...

  • Page 64: Precautions

    TXZ Family Serial Peripheral Interface Precautions ● In case of the product which does not have TSPIxCS0/1/2/3 terminals or TSPIxCSIN terminal, please use SIO mode that is not using these terminals. ● Do not access the address that is not assigned register. 2019-02-28 64 / 67 Rev.

  • Page 65: Revision History

    TXZ Family Serial Peripheral Interface Revision History Table 7.1 Revision History Revision Date Description 2017-09-11 First release -1.Outline: Corrected “(synchronous serial communication)” to “(Serial Peripheral Interface)”. Modified description in DMA request in Table1.1/1.2/1.3/1.4. Modified “Minimum idle time…” to “Idle time…” in Table1.1/1.3 Modified TSPIxCS0/1/2/3 deassertion delay "final"-->"last"...
  • Page 66 TXZ Family Serial Peripheral Interface -4.2.6. [TSPIxFMTR0]: Modified to "This setup…of <FINT> occurs." in <FINT>. Corrected to "Polarity of serial clock" to "Polarity of idle period of serial clock (Note2)" in <CKPOL>. Modified "Minimum idle time" to "Idle time" and to "CS deassertion…in master mode.”...

  • Page 67: Restrictions On Product Use

    Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook"...

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