Toshiba TLCS-900/H1 Series Manual page 85

Sample 1: Calculation example for CPU + HDMA
Conditions:
CPU operation speed (f
I S sampling frequency
2
I S data transfer bit length
2
DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I
Calculation example:
DMAC source data read time:
Internal RAM data read time
= 1 state/4 bytes (However, the first 1 byte requires 2 states.)
DMAC destination write time:
I S register write time = 2 states/4 bytes
2
Transfer count
To transfer 5 Kbytes of data in 4-byte units, the transfer count is calculated as
follows:
5 Kbytes/4 bytes = 1280 [times]
Since I S generates an interrupt for every 64 bytes, the DMAC's counter A is set to
2
16 (64 bytes/4 bytes = 16 times) and counter B is set to 80.
Note: Since an interrupt is generated 80 times, the first read to internal RAM (which requires 1 additional state) occurs
80 times, requiring additional 80 states in total. In addition, from bus REQ to bus ACK, an overhead time of 2
states is also needed for each interrupt request, requiring additional 160 states in total.
t (HDMA) = (((1 + 2) × 16) × 80) + 80 + 160) / f
STOP
HDMA start interval [s] = 1 / I
CPU bus stop rate = t
) : 60 MHz
SYS
: 48 kHz (60 MHz/25/50 = 48 kHz)
: 16 bits
S sampling frequency [Hz] × (64 / 16 )
2
= 83.33 [ms]
(HDMA) [s] / HDMA start interval [s]
STOP
= 68 [μs] / 83.33 [ms] = 0.08 [%]
92CF30-83
TMP92CF30
S
2
[s] = 68 [μs]
SYS
2009-06-12