Interrupt Controller - Toshiba TLCS-90 Series Data Book

TOSHIBA TMP90C840
3.3.3 Interrupt controller
Fig. 3.3 (8) outlines the interrupt circuit. The left side of this
figure represents an interrupt controller, and the right side
comprises the CPU's interrupt request signal circuit arid HALT release
signal circuit (See "3.4 Standby Function" for the HALT operation).
The interrupt controller consists of Interrupt Request Flip-flops,
interrupt enable flags, and micro DMA enable flags allocated to each
of 14 channels. The Interrupt Request Flip-flops serve to latch
inter~upt
requests from peripherals. Each flip-flop is reset to "0"
when a reset or interrupt is acknowledged by the CPU and the vector of
the interrupt channel is read into the CPU, or when the CPU executes
an instruction that clears a request to interrupt that channel (write
"vector divided by 8" into the memory address FFC3H). For example, by
executing
LD (FFC3H), s8Hi8,
the Interrupt Request Flip-flops for the interrupt channel "INTI"
whose vector is 58H is reset to "0".
The status of an Interrupt Request Flip-flops is found out by reading
the memory address FFC2H or FFC3H. "0" denotes there is no interrupt
request, and "1" denotes that an interrupt is requested. Fig. 3.3
(7)
illustrates the bit configuration indicating the status of Interrupt
Request Flip-flops.
IRFL


____
~/_IR~F~O~/~IR~F~T~O~I_IR~F_T~l~I
____
~E~XT
__
~IP~I~C~R~1P~O~C
__ R
(FFC2H)
I
I See "3.5.2 Port 1".
I
I_R ___
>
INTT 1 req ue s t flag
________ R ___
>
INTTO request flag
______________ R ___
>
INTO request flag
IRFH IIRFT21IRFT31IRFT41IRFI /IRFT5IIRF2 I IRFRXI IRFTXI
(FFC3H)
I
I
~>
R
>
R
>
R
>
R
>
R
>
R
>
R
>
INTTX req uest flag
INTRX request flag
INT2 req uest flag
INTTS req uest flag
INTI request flag
INTT4 req uest flag
INTT3 req uest flag
INTT2/INTAD request
flag
(Caution) Writing "vector divided by 8" into the memory address FFC3H
clears the Flip-flop for the specified interrupt request.
Fig. 3.3 (7) Configuration of Interrupt Request Flip-flops
MPU90-45